MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1428

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Universal Serial Bus Interfaces
one of the following events occur: The transaction translator responds to a complete-split transaction with
one of the following:
Each time the host controller visits a queue head in this state (once within the Execute Transaction state),
bit-wise ANDs QH[S-mask] with cMicroFrameBit to determine whether to execute a start-split. If the
result is non-zero, then the host controller issues a start-split transaction. If the PID Code field indicates
an IN transaction, the host controller must zero-out the QH[S-bytes] field. After the split-transaction has
been executed, the host controller sets up state in the queue head to track the progress of the complete-split
phase of the split transaction. Specifically, it records the expected frame number into QH[FrameTag] field,
sets C-prog-mask to zero (0x00), and exits this state. Note that the host controller must not adjust the value
of Cerr as a result of completion of a start-split transaction.
21.6.12.2.7 Periodic Interrupt—Do-Complete-Split
This state is entered unconditionally from the Do Start Split state after a start-split transaction is executed
on the bus. Each time the host controller visits a queue head in this state (once within the Execute
Transaction state), it checks to determine whether a complete-split transaction should be executed now.
There are four tests to determine whether a complete-split transaction should be executed.
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NAK. A NAK response is a propagation of the full- or low-speed endpoint's NAK response.
ACK. An ACK response is a propagation of the full- or low-speed endpoint's ACK response. Only
occurs on an OUT endpoint.
DATA 0/1. Only occurs for INs. Indicates that this is the last of the data from the endpoint for this
split transaction.
ERR. The transaction on the low-/full-speed link below the transaction translator had a failure (for
example, timeout, bad CRC, etc.).
NYET (and Last). The host controller issued the last complete-split and the transaction translator
responded with a NYET handshake. This means that the start-split was not correctly received by
the transaction translator, so it never executed a transaction to the full- or low-speed endpoint, see
Section Periodic Interrupt - Do Complete Split for the definition of 'Last'.
Test A. cMicroFrameBit is bit-wise ANDed with QH[C-mask] field. A non-zero result indicates
that software scheduled a complete-split for this endpoint, during this micro-frame.
Test B. QH[FrameTag] is compared with the current contents of FRINDEX[7–3]. An equal
indicates a match.
Test C. The complete-split progress bit vector is checked to determine whether the previous bit is
set, indicating that the previous complete-split was appropriately executed. An example algorithm
for this test is provided below:
Algorithm Boolean CheckPreviousBit(QH.C-prog-mask, QH.C-mask, cMicroFrameBit)
Begin
-- Return values:
-- TRUE - no error
-- FALSE - error
--
Boolean rvalue = TRUE;
previousBit = cMicroframeBit logical-rotate-right(1)
-- Bit-wise anding previousBit with C-mask indicates
-- whether there was an intent
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Freescale Semiconductor