MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1403

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

accomplished by incrementing FRINDEX[13–3] based on carry-out on the 7 to 0 increment of
FRINDEX[2–0] and incrementing SOFV based on the transition of 0 to 1 of FRINDEX[2–0].
Software is allowed to write to FRINDEX.
provides the requirements that software should adhere when writing a new value in FRINDEX.
21.6.7
The periodic schedule traversal is enabled or disabled through USBCMD[PSE] (periodic schedule enable).
If USBCMD[PSE] is cleared, then the host controller simply does not try to access the periodic frame list
via the PERIODICLISTBASE register. Likewise, when USBCMD[PSE] is a one, then the host controller
does use the PERIODICLISTBASE register to traverse the periodic schedule. The host controller will not
react to modifications to USBCMD[PSE] immediately. In order to eliminate conflicts with split
transactions, the host controller evaluates USBCMD[PSE] only when FRINDEX[2–0] is zero. System
software must not disable the periodic schedule if the schedule contains an active split transaction work
item that spans the 0b000 micro-frame. These work items must be removed from the schedule before
USBCMD[PSE] is cleared. USBSTS[PS] (periodic schedule status) indicates status of the periodic
schedule. System software enables (or disables) the periodic schedule by setting (or clearing)
USBCMD[PSE]. Software then can poll USBSTS[PS] to determine when the periodic schedule has made
the desired transition. Software must not modify USBCMD[PSE] unless the value of USBCMD[PSE]
equals that of USBSTS[PS].
The periodic schedule is used to manage all isochronous and interrupt transfer streams. The base of the
periodic schedule is the periodic frame list. Software links schedule data structures to the periodic frame
list to produce a graph of scheduled data structures. The graph represents an appropriate sequence of
transactions on the USB.
period of one are linked directly to the periodic frame list. Interrupt transfers (are managed with queue
heads) and isochronous streams with periods other than one are linked following the period-one
iTD/siTDs. Interrupt queue heads are linked into the frame list ordered by poll rate. Longer poll rates are
linked first (for example, closest to the periodic frame list), followed by shorter poll rates, with queue
heads with a poll rate of one, on the very end.
Freescale Semiconductor
FRINDEX[13–3]
Periodic Schedule
N+1
N+1
N+1
N+1
N+1
N+1
N+1
N
Table 21-64. Operation of FRINDEX and SOFV (SOF Value Register)
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Figure 21-46
Current
SOFV
N+1
N+1
N+1
N+1
N+1
N+1
N
N
FRINDEX[2–0]
illustrates isochronous transfers (using iTDs and siTDs) with a
111
000
001
010
011
100
101
110
Section 21.3.2.4, “Frame Index Register (FRINDEX),”
FRINDEX[13–3]
N+1
N+1
N+1
N+1
N+1
N+1
N+1
N+1
SOFV
Next
N+1
N+1
N+1
N+1
N+1
N+1
N+1
N
Universal Serial Bus Interfaces
FRINDEX[2–0]
000
001
010
011
100
101
110
111
21-69