MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1399

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

System software observes the resume event on the port, delays a port resume time (nominally 20
milliseconds), then terminates the resume sequence by clearing PORTSC[FPR] in the port. The host
controller receives the write of zero to PORTSC[FPR], terminates the resume sequence and clears
PORTSC[FPR] and PORTSC[SUSP]. Software can determine that the port is enabled (not suspended) by
sampling the PORTSC register and observing that the SUSP and FPR bits are zero. Software must ensure
that the host controller is running (that is, USBSTS[HCH] is a zero), before terminating a resume by
clearing the port's PORTSC[FPR] bit. If HCH is a one when PORTSC[FPR] is cleared, then SOFs will not
occur down the enabled port and the device will return to suspend mode in a maximum of 10 milliseconds.
Table 21-63
If USBINTR[PCE] (port change interrupt enable) is a one, the host controller also generates an interrupt
on the resume event. Software acknowledges the resume event interrupt by clearing the USBSTS[PCI].
Freescale Semiconductor
Port disabled, resume K-State received
Port suspended, Resume K-State
received
Port is enabled, disabled or suspended,
and the port's WKDSCNNT_E bit,
PORTSC[WKDS], is set. A disconnect is
detected.
Port is enabled, disabled or suspended,
and the port's WKDSCNNT_E bit,
PORTSC[WKDS], is cleared. A
disconnect is detected.
Port is not connected and the port's
WKCNNT_E bit is a one. A connect is
detected.
Port is not connected and the port's
WKCNNT_E bit is a zero. A connect is
detected.
Port is connected and the port's
WKOC_E bit is a one. An over-current
condition occurs.
Port is connected and the port's
WKOC_E bit is a zero. An over-current
condition occurs.
1
2
3
Hardware interrupt issued if USBINTR[PCE] (port change interrupt enable) is set.
PME# asserted if enabled (Note: PME Status must always be set).
PME# not asserted.
Port Status and Signaling Type
summarizes the wake-up events. Whenever a resume event is detected, USBSTS[PCI] is set.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 21-63. Behavior During Wake-up Events
No effect
Resume reflected downstream on signaled port.
PORTSC[FPR] is set. USBSTS[PCI] is set.
Depending on the initial port state, the PORTSC Connect
(CCS) and Enable (PE) status bits are cleared, and the
Connect Change status bit (CSC) is set. USBSTS[PCI] is set.
Depending on the initial port state, the PORTSC Connect
(CCS) and Enable (PE) status bits are cleared, and the
Connect Change status bit (CSC) is set. USBSTS[PCI] is set.
PORTSC Connect Status (CCS) and Connect Status Change
(CSC) bits are set. USBSTS[PCI] is set.
PORTSC Connect Status (CCS) and Connect Status Change
(CSC) bits are set. USBSTS[PCI] is set.
PORTSC Over-current Active (OCA), Over-current Change
(OCC) bits are set. If Port Enable/Disable bit (PE) is a one, it is
cleared. USBSTS[PCI] is set
PORTSC Over-current Active (OCA), Over-current Change
(OCC) bits are set. If Port Enable/Disable bit (PE) is a one, it is
cleared. USBSTS[PCI] is set.
Signaled Port Response
Universal Serial Bus Interfaces
[1], [2]
[1], [2]
[1], [3]
[1], [2]
[1], [3]
[1], [2]
[1], [3]
N/A
D0
Device State
not D0
N/A
[2]
[2]
[3]
[2]
[3]
[2]
[3]
21-65