MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1498

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Global Utilities
Table 23-4
23.4.1.2
The PORBMSR, shown in
mode settings (described in
23-6
10–15
17–25
26–30
Bits
0–1
2–6
7–9
16
31
PCI_clk_sel Clock used for PCI. This bit corresponds to the values on cfg_pci_clk_sel at the negation of HRESET:
DDR_Ratio
e500_Ratio
Plat_Ratio
describes the bit settings of PORPLLSR.
Name
POR Boot Mode Status Register (PORBMSR)
—
—
—
—
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Reserved
Clock ratio between the DDR Complex clock and DDRCLK. Patterns not show are reserved
00011
00100
00110
01000
Reserved
Clock ratio between the e500 core and the CCB clock. Initially, the 3 lsbs of this field correspond to
the values on cfg_core_pll[0:2]. However, this register reflects the current clock ratio between the e500
core and the CCB clock, and therefore if this ratio is changed by moifying PMJCR[e500_Ratio] and
executing a Deep Sleep or Jog request, then this field may not necessarily reflect the values on
cfg_core_pll[0:2].
Patterns not shown are reserved.
000010 Reserved
000011 3:2
000100 2:1
000101 5:2
0 PCI runs off of PCI_CLK
1 PCI runs off of SYSCLK
Reserved
Clock ratio between the CCB (platform) clock and SYSCLK. Patterns not shown are reserved.
00011
00100
00101
00110
Reserved
Figure
Section 4.4.3.6, “Boot ROM Location,” Section 4.4.3.10, “CPU Boot
3:1
4:1
6:1
8:1
3:1
4:1
5:1
6:1
Table 23-4. PORPLLSR Field Descriptions
23-2, reports setting of the POR configuration pins that control the boot
Description
01010
01100
01110
00111
000110 3:1
000111 7:2
001000 4:1
001001 9:2
01000
01001
01010
01100
11101
Clocked by CCB clock
10:1
12:1
Reserved
Synchronous Mode-DDR Complex
8:1
9:1
10:1
12:1
20:1
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