MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1539

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

23.5
This section describes the global utilities from a functional perspective.
23.5.1
The PMC is responsible for maintaining the device in various low power modes.
23.5.1.1
MPC8536E supports minimizing the power consumption at several levels.
MPC8536E supports a deep sleep mode where power is removed to a portion of the die.
The PMC can gracefully stop the internal system bus and direct the memory controller to put DDR into
self-refresh (if enabled).
In addition, the PMC controls the external power regulator switch to disable the VDD from a portion of
the die.
Freescale Semiconductor
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24–25
26–31 SDTXLE Controls lane E transmitter amplitude levels.
Bits
Dynamic power management
Shutting down unused blocks
Software controlled power-down state (doze, nap, sleep, deep sleep)
Functional Description
Power Management Controller (PMC)
Name
Overview
—
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Reserved
If SRDS2CR0[23] = 0, then Full Swing = Vdd/2 and bit settings are as follows:
bits [26–28] = Reserved
000 No amplitude reduction
001 0.916
010 0.833
011 0.750
100 0.666
101 0.583
110 0.500
111 Reserved
If SRDS2CR0[23] = 1, then Full Swing = 5/6 * Vdd/2 and bit settings are as follows:
bits [26–28] = Reserved
000 No amplitude reduction
001 0.916
010 0.833
011 0.750
100 0.666
101 0.583
110 0.500
111 Reserved
Recommended setting per protocol:
• SGMII: 000
• SATA: 101
Table 23-36. SRDS2CR3 Field Descriptions (continued)
full swing
full swing
full swing
full swing
full swing
full swing
full swing
full swing
full swing
full swing
full swing
full swing
Description
Global Utilities
23-47