MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 506

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Security Engine (SEC) 3.0
Context and Operation for CCM Encryption/MAC Generation
The context for CCM encryption/MAC generation (shown in
Using the session-specific key and context described above, operation of the AESU for CCM
encryption/MAC generation requires the following steps (note these steps are performed automatically in
channel-driven access):
10-76
•
•
•
•
1. Initialize the IV, and encrypt with the symmetric key.
2. In CBC fashion, take the output of step 1, hash with the first block of plaintext, and encrypt with
3. Continue as in step 2 until the final block of plaintext has been processed. The result of the
4. The first item to be encrypted in counter cipher mode is the counter (initial counter value) from
Encrypt
(outbound)
Decrypt
(inbound)
Registers 1–2 contain the session-specific 128-bit initialization vector (from memory)
Registers 3–4 contain 128 bits of zero padding
Registers 5–6 contain the session specific initial counter value (from memory)
Register 7 contains the counter modulus exponent.
Several current standards require a counter modulus exponent of 128 for CCM cipher
mode. However, in order to support possible new standards the counter modulus exponent
in AESU is a programmable field, which must be generated and stored along with other ses-
sion-specific information for loading into the AESU context register prior to CCM
encryption.
the symmetric key.
encryption of the final block of plaintext with the symmetric key is the MAC tag. The full 128 bits
of MAC data is written to context registers 1–2, for use in the next phase of CCM processing. Once
the MAC tag has been generated (step 3), the MAC tag along with the plaintext is encrypted with
the AESU operating in counter cipher mode.
context registers 5–6. The counter is encrypted with the symmetric key, and the result is hashed
with the MAC tag (retrieved from context registers 1–2) to produce the MIC (encrypted MAC),
which is then stored in context registers 3–4. At the completion of CCM encrypt processing, this
MIC is output to memory (per the descriptor pointer) for the host to append to the 802.11i frame.
Outputs
Outputs Computed
Inputs
Inputs
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
MAC
MAC
1
Figure 10-30. AESU CCM Context Registers
IV
IV
2
0
0
Decrypted
MAC
MIC
MIC
3
0
Context Registers
4
0
0
0
Figure
Initial Counter Value
Initial Counter
5
10-30) is as follows:
6
Counter Modulus
Counter Modulus
Freescale Semiconductor
Exponent
Exponent
7