MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1362

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Universal Serial Bus Interfaces
21-28
Bits
6
5
4
3
Name
OCC
OCA
PEC
FPR
Force port resume. This bit is not-EHCI compatible.
1 Resume detected/driven on port.
0 No resume (K-state) detected/driven on port.
Host mode:
Device mode:
Over-current change. This bit gets set when there is a change to over-current active. Software clears this bit
by writing a one to this bit position.
Host mode:
Device mode:
1 Over current detect.
0 No over current.
Over-current active. This bit will automatically transition from one to zero when the over current condition is
removed.
Host mode:
Device mode:
1 Port currently in over-current condition.
0 Port not in over-current condition.
Port enable/disable change
For the root hub, this bit gets set only when a port is disabled due to disconnect on the port or due to the
appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification). Software clears
this by writing a one to it.
Device mode:
1 Port disabled.
0 No change.
This field is zero if Port Power(PP) is zero.
• Software sets this bit to one to drive resume signaling. The controller sets this bit to one if a J-to-K transition
• Note that when the controller owns the port, the resume sequence follows the defined sequence
• This field is zero if Port Power (PP) is zero in host mode.
• After the device has been in Suspend State for 5 msec or more, software must set this bit to one to drive
• The user can provide over-current detection to the USB n _PWRFAULT signal for this condition.
• This bit must always be 0.
• The user can provide over-current detection to the USB n _PWRFAULT signal for this condition.
• This bit must always be 0.
• The device port is always enabled. (This bit will be zero).
is detected while the port is in the Suspend state. When this bit transitions to a one a J-to-K transition is
detected, USBSTS[PCI] (port change detect) is also set. This bit will automatically change to zero after the
resume sequence is complete. This behavior is different from EHCI where the host controller driver is
required to set this bit to a zero after the resume duration is timed in the driver.
documented in the USB Specification Revision 2.0. The resume signaling (Full-speed ‘K’) is driven on the
port as long as this bit remains a one. This bit will remain a one until the port has switched to the high-speed
idle. Writing a zero has no affect because the port controller will time the resume operation clear the bit the
port control state switches to HS or FS idle.
resume signaling before clearing. The USB controller will set this bit to one if a J-to-K transition is detected
while the port is in the Suspend state. The bit will be cleared when the device returns to normal operation.
Also, when this bit transitions to a one because a J-to-K transition detected, USBSTS[PCI] is also set.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 21-22. PORTSC Register Field Descriptions (continued)
Description
Freescale Semiconductor