MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 594

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

I
11.1.1
The two-wire I
bus allows the connection of additional devices to the bus for expansion and system development. The bus
includes collision detection and arbitration that prevent data corruption if two or more masters attempt to
control the bus simultaneously.
11.1.2
The I
11.1.3
The I
11-2
2
C Interfaces
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2
2
C interface includes the following features:
C units on this device can operate in one of the following modes:
Two-wire interface
Multiple-master operation
Arbitration lost interrupt with automatic mode switching from master to slave
Calling address identification interrupt
START and STOP signal generation/detection
Acknowledge bit generation/detection
Bus busy detection
Software-programmable clock frequency
Software-selectable acknowledge bit
On-chip filtering for spikes on the bus
Master mode—The I
address. The I
Slave mode—The I
START condition from a non-I
Interrupt-driven byte-to-byte data transfer—When successful slave addressing is achieved (and
SCL returns to zero), the data transfer can proceed on a byte-to-byte basis in the direction specified
by the R/W bit sent by the calling master. Each byte of data must be followed by an acknowledge
bit, which is signaled from the receiving device. Several bytes can be transferred during a data
transfer session.
Boot sequencer mode—This mode can be used to initialize the configuration registers in the device
after the I
disabled as a default, but this mode can be selected with the cfg_boot_seq[0:1] power-on reset
(POR) configuration signals that are located on the LGPL3 and LGPL5 signals.
Overview
Features
Modes of Operation
2
C bus minimizes interconnections between devices. The synchronous, multiple-master I
2
C1 module is initialized. Note that the device powers up with boot sequencer mode
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
2
C cannot be a master and a slave simultaneously.
2
2
C is not the driver of the SDA line. The module must be enabled before a
C is the driver of the SDA line. It cannot use its own slave address as a calling
2
C master is detected.
Freescale Semiconductor
2
C