MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 305

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale Semiconductor
Bits
2–3
1–3
5–7
0
1
4
8
9
SET_REF Set refresh. Forces an immediate refresh to be issued to the chip select specified by
SET_PRE Set precharge. Forces a precharge or precharge all to be issued to the chip select specified by
MD_SEL
CS_SEL
CS_SEL
MD_EN
Name
—
—
Mode enable. Setting this bit specifies that valid data in MD_VALUE is ready to be written to DRAM as one
of the following commands:
The specific command to be executed is selected by setting MD_SEL. In addition, the chip select must be
chosen by setting CS_SEL. MD_EN is set by software and cleared by hardware once the command has
been issued.
0 Indicates that no mode register set command needs to be issued.
1 Indicates that valid data contained in the register is ready to be issued as a mode register set command.
Reserved
Select chip select. Specifies the chip select that is driven active due to any command forced by software in
DDR_SDRAM_MD_CNTL.
00 Chip select 0 is active
01 Chip select 1 is active
10 Chip select 2 is active
11 Chip select 3 is active
Select chip select. Specifies the chip select that is driven active due to any command forced by software in
DDR_SDRAM_MD_CNTL.
000 Chip select 0 is active
001 Chip select 1 is active
010 Chip select 2 is active
011 Chip select 3 is active
100 Chip select 0 and chip select 1 are active
101 Chip select 2and chip select 3 are active
110-111Chip select 3 is active
Reserved
Mode register select. MD_SEL specifies one of the following:
Note that MD_SEL contains the value that is presented onto the memory bank address pins (MBA n ) of the
DDR controller.
000 MR
001 EMR
010 EMR2
011 EMR3
DDR_SDRAM_MD_CNTL[CS_SEL]. This bit is set by software and cleared by hardware once the
command has been issued.
0 Indicates that no refresh command needs to be issued.
1 Indicates that a refresh command is ready to be issued.
DDR_SDRAM_MD_CNTL[CS_SEL]. This bit is set by software and cleared by hardware once the
command has been issued.
0 Indicates that no precharge all command needs to be issued.
1 Indicates that a precharge all command is ready to be issued.
• MODE REGISTER SET
• EXTENDED MODE REGISTER SET
• EXTENDED MODE REGISTER SET 2
• EXTENDED MODE REGISTER SET 3
• During a mode select command, selects the SDRAM mode register to be changed
• During a precharge command, selects the SDRAM logical bank to be precharged. A precharge all
• During a refresh command, this field is ignored.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
command ignores this field.
Table 8-17. DDR_SDRAM_MD_CNTL Field Descriptions
Description
DDR Memory Controller
8-31