MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 587

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.7.8.4
This RNGU status register,
signals.
The RNGU status register is read only. Writing to this location results in an address error being reflected
in the RNGU interrupt status register.
Table 10-73
Freescale Semiconductor
Offset 0x3_A028
Reset
W
R
40–47
48–57
8–63
0–39
0-60
Bits
Bits
61
62
63
0
describes RNGU status register fields.
RNGU Status Register
Name
Name
OFL
SR
MI
—
RI
—
—
—
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 10-72. RNGU Reset Control Register Field Descriptions
Table 10-73. RNGU Status Register Field Descriptions
Reserved
Reset Interrupt. Writing this bit active high causes RNGU interrupts signaling done and
error to be reset. It further resets the state of the RNGU interrupt status register.
0 No reset
1 Reset interrupt logic
Module Initialization. This reset value performs enough of a reset to prepare the RNGU for
another request, without forcing the internal control machines and the output FIFO to be
reset, thereby invalidating stored random numbers or requiring reinvocation of a warm-up
period. Module initialization is nearly the same as software reset, except that the interrupt
mask register remains unchanged.
0 No reset
1 Reset most of RNGU
Software reset is functionally equivalent to hardware reset (the RESET# pin), but only for
the RNGU. All registers and internal state are returned to their defined reset state.
0 No reset
1 Full RNGU reset
Reserved
Reserved
The number of dwords currently in the output FIFO
Reserved
Figure
—
Figure 10-106. RNGU Status Register
10-106, contains 6 fields that reflect the state of the RNGU internal
All zeros
39 40
Description
Description
OFL
47 48
—
57
HALT
58
Security Engine (SEC) 3.0
59
—
Access: Read only
60
EI DI
61
62
10-157
RD
63