MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1536

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Global Utilities
23.4.1.33 SerDes2 Control Register 3 (SRDS2CR3)
Shown in
23-44
Offset 0xE_310C
Reset
Reset
24–26
27–31
Bits
W
W
R
R
16
0
0
Figure
—
—
Name
EICE
—
17
0
1
23-33, the SRDS2CR3 contains the functional control bits for the SerDes2 logic.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Reserved
SATA receiver electrical idle detection control for lane E.
Settings for bits 27–29:
000 Loss of signal detect function is disabled.
001 Default SGMII levels (low = 30 mV, high = 100 mV)
010 Intermediate level (low = 38 mV, high = 120 mV)
011 Intermediate level (low = 50 mV, high = 150 mV)
100 SATA1 levels (low = 65 mV, high = 175 mV)
101 Default SATA2 levels (low = 75 mV, high = 200 mV)
110 Intermediate level (low = 88 mV, high = 225 mV)
111 Intermediate level (low = 100mV, high = 250 mV)
Recommended setting per protocol:
Settings for bits 30–31:
For SGMII:
00 Exit from Idle ~88UI and Unexpected Idle Detect ~1us (Application Mode)
01 Exit from Idle ~88UI and Unexpected Idle Detect ~10us
10 Exit from Idle ~48UI and Unexpected Idle Detect ~1us
11 Bypass
For SATA:
00 20 consecutive UI with no glitch (for exit from idle and for loss of signal detection).
01 40 consecutive UI with no glitch (for exit from idle and for loss of signal detection).
10 80 consecutive UI with no glitch (for exit from idle and for loss of signal detection).
11 20 consecutive UI with no glitch (for exit from idle and for loss of signal detection).
Recommended setting per protocol:
18
0
2
• SGMII: 001
• SATA: 101
• SGMII: 00
• SATA: 00
KFRA
Table 23-35. SRDS2CR2 Field Descriptions (continued)
Figure 23-33. SerDes2 Control Register 3 (SRDS2CR3)
3
0
0
SDTXLA
4
KPHA
5
0
0
6
SDFMA
23
7
1
All zeros
Description
24
0
8
—
—
25
0
9
10
26
0
KFRE
11
0
12
0
SDTXLE
Freescale Semiconductor
KPHE
Access: Read/Write
13
0
14
0
SDFME
15
31
1