MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1289

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale Semiconductor
PEROFF
HCKOFF
IPGOFF
SDOFF
Field
WTA
RTA
22
23
24
25
26
27
28
Read transfer active. This status is used for detecting completion of a read transfer.
This bit is set for either of the following conditions:
This bit is cleared for either of the following conditions:
0 No valid data
1 Transferring data
Write transfer active. This status indicates a write transfer is active. If this bit is 0, it means no valid write data exists
in eSDHC.
This bit is set in either of the following cases:
This bit is cleared in either of the following cases:
During a write transaction, a IRQSTAT[BGE] interrupt is generated when this bit is changed to 0, as result of
PROCTL[SABGREQ] being set. This status is useful for the host driver in determining when to issue commands
during write busy.
0 No valid data
1 Transferring data
SD clock gated off internally. Indicates the SD clock is internally gated off because of a buffer overrun, buffer
underrun, or a read pause without read-wait assertion. This bit is for the host driver to debug data transaction on SD
bus.
This status bit resets to 0, but reflects the value of the automatic clock gating and may transition to 1 if the eSDHC
is idle.
The internal bus clock gated off internally. This status bit indicates the internal bus clock is internally gated off. This
bit is for the host driver to debug a transaction on SD bus.
This status bit resets to 0, but reflects the value of the automatic clock gating and may transition to 1 if the eSDHC
is idle.
Master clock gated off internally. This status bit indicates master clock is internally gated off. This bit is for the host
driver to debug a data transfer.
This status bit resets to 0, but reflects the value of the automatic clock gating and may transition to 1 if the eSDHC
is idle.
Controller clock gated off internally. Indicates that the controller clock is internally gated off. This bit is for the host
driver to debug.
This status bit resets to 0, but reflects the value of the automatic clock gating and may transition to 1 if the eSDHC
is idle.
Reserved
• After the end bit of the read command
• When writing a 1 to PROCTL[CREQ] to restart a read transfer
• When the last data block as specified by block length is transferred to the system
• When all valid data blocks have been transferred to the system and no current block transfers are being sent as
• After the end bit of the write command.
• When writing a 1 to PROCTL[CREQ] to restart a write transfer.
• After getting the CRC status of the last data block, as specified by the transfer count (single and multiple)
• After getting the CRC status of any block where data transmission is about to be stopped by a stop-at-block-gap
a result of PROCTL[SABGREQ] being set. A transfer complete interrupt is generated when this bit changes to 0.
request.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 20-11. PRSSTAT Field Descriptions (continued)
Description
Enhanced Secure Digital Host Controller
20-15