MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1412

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Universal Serial Bus Interfaces
Alternatively, a host controller implementation is allowed to traverse the entire asynchronous schedule list
(for example, observed the head of the queue (twice)) before setting USBSTS[AAI].
Software may re-use the memory associated with the removed queue heads after it observes
USBSTS[AAI] is set, following assertion of the doorbell. Software should acknowledge the interrupt on
async advance status as indicated in the USBSTS register, before using the doorbell handshake again
21.6.9.3
EHCI uses two bits to detect when the asynchronous schedule is empty. The queue head data structure (see
Figure
the head of the reclaim list. host controller also keeps a 1-bit flag in the USBSTS register (Reclamation)
that is cleared when the host controller observes a queue head with the H-bit set. The reclamation flag in
the status register is set when any USB transaction from the asynchronous schedule is executed (or
whenever the asynchronous schedule starts, see
Start Event.”
If the controller ever encounters an H-bit of one and a Reclamation bit of zero, the controller simply stops
traversal of the asynchronous schedule.
21-78
21-40) defines an H-bit in the queue head, which allows software to mark a queue head as being
HC State
A
A
Empty Asynchronous Schedule Detection
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Memory State
Before Unlink
B
Async-Advance Doorbell = 0
Figure 21-48. Generic Queue Head Unlink Scenario
USBCMD Interrupt on
C
HC State
D
A
USBSTS Interrupt on Async-Advance = 1
D
Async-Advance Doorbell = 0
Memory State
After Doorbell
B
USBCMD Interrupt on
Section 21.6.9.4, “Asynchronous Schedule Traversal:
C
HC State
A
A
After Unlink (B, C) and at Doorbell
USBSTS Interrupt on Async-Advance = 0
D
Async-Advance Doorbell = 1
Memory State
B
USBCMD Interrupt on
C
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D