MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 26

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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14.5.3.6.27
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14.5.3.6.33
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14.5.3.6.35
14.5.3.6.36
14.5.3.6.37
14.5.3.6.38
14.5.3.6.39
14.5.3.6.40
14.5.3.6.41
14.5.3.6.42
14.5.3.6.43
14.5.3.6.44
14.5.3.6.45
14.5.3.6.46
14.5.3.6.47
14.5.3.6.48
14.5.3.7
14.5.3.7.1
14.5.3.7.2
14.5.3.8
14.5.3.8.1
14.5.3.9
14.5.3.9.1
14.5.3.9.2
14.5.3.10
14.5.3.10.1
14.5.3.10.2
14.5.3.11
14.5.3.11.1
14.5.3.11.2
14.5.3.11.3
14.5.3.11.4
14.5.3.11.5
14.5.3.11.6
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MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Hash Function Registers .................................................................................... 14-115
FIFO Registers................................................................................................... 14-116
DMA Attribute Registers................................................................................... 14-118
Lossless Flow Control Configuration Registers ................................................ 14-120
Hardware Assist for IEEE1588 Compliant Timestamping................................ 14-122
Transmit Multicast Packet Counter (TMCA) ................................................ 14-101
Transmit Broadcast Packet Counter (TBCA) ................................................ 14-101
Transmit Pause Control Frame Counter (TXPF)........................................... 14-102
Transmit Deferral Packet Counter (TDFR) ................................................... 14-102
Transmit Excessive Deferral Packet Counter (TEDF) .................................. 14-103
Transmit Single Collision Packet Counter (TSCL) ....................................... 14-103
Transmit Multiple Collision Packet Counter (TMCL) .................................. 14-104
Transmit Late Collision Packet Counter (TLCL) .......................................... 14-104
Transmit Excessive Collision Packet Counter (TXCL)................................. 14-105
Transmit Total Collision Counter (TNCL) .................................................... 14-105
Transmit Drop Frame Counter (TDRP)......................................................... 14-106
Transmit Jabber Frame Counter (TJBR) ....................................................... 14-106
Transmit FCS Error Counter (TFCS) ............................................................ 14-107
Transmit Control Frame Counter (TXCF)..................................................... 14-107
Transmit Oversize Frame Counter (TOVR) .................................................. 14-108
Transmit Undersize Frame Counter (TUND)................................................ 14-108
Transmit Fragment Counter (TFRG)............................................................. 14-109
Carry Register 1 (CAR1) ............................................................................... 14-109
Carry Register 2 (CAR2) ................................................................................14-111
Carry Mask Register 1 (CAM1) .................................................................... 14-112
Carry Mask Register 2 (CAM2) .................................................................... 14-113
Receive Filer Rejected Packet Counter (RREJ) ............................................ 14-114
Individual/Group Address Registers 0–7 (IGADDRn) ................................. 14-115
Group Address Registers 0–7 (GADDRn) .................................................... 14-116
FIFO Configuration Register (FIFOCFG)..................................................... 14-116
Attribute Register (ATTR)............................................................................. 14-118
Attribute Extract Length and Extract Index Register (ATTRELI) ............... 14-119
Receive Queue Parameters 0–7 (RQPRM0–PQPRM7) ................................ 14-120
Receive Free Buffer Descriptor Pointer Registers 0–7
Timer Control Register (TMR_CTRL) ......................................................... 14-122
Timer Event Register (TMR_TEVENT) ....................................................... 14-124
Timer Event Mask Register (TMR_TEMASK) ............................................ 14-125
Timer PTP Packet Event Register (TMR_PEVENT) .................................... 14-126
Timer Event Mask Register (TMR_PEMASK) ............................................ 14-127
Timer Status Register (TMR_STAT) ............................................................. 14-128
(RFBPTR0–RFBPTR7) ............................................................................. 14-121
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