MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1082

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PCI Bus Interface
it asserts PCI_STOP, indicating that the target can accept the current data, but no more data can be
transferred. For disconnect-without-data, the target asserts PCI_STOP when PCI_TRDY is negated
indicating that the target cannot accept any more data.
16.4.2.9
Fast Back-to-Back Transactions
The PCI bus allows fast back-to-back transactions by the same master. During a fast back-to-back
transaction, the initiator starts the next transaction immediately without an idle state. The last data phase
completes when PCI_FRAME is negated, and PCI_IRDY and PCI_TRDY are asserted. The current
master starts another transaction in the clock cycle immediately following the last data transfer for the
previous transaction.
Fast back-to-back transactions must avoid contention on the PCI_TRDY, PCI_DEVSEL, PCI_PERR, and
PCI_STOP signals. There are two types of fast back-to-back transactions—those that access the same
target and those that access multiple targets sequentially. The first type places the burden of avoiding
contention on the initiator; the second type places the burden of avoiding contention on all potential
targets.
As an initiator, the PCI controller does not perform any fast back-to-back transactions. As a target, the PCI
controller supports both types of fast back-to-back transactions.
During fast back-to-back transactions, the PCI controller monitors the bus states to determine if it is the
target of a transaction. If the previous transaction was not directed to the PCI controller but the current
transaction is directed at the PCI controller, it delays the assertion of PCI_DEVSEL (as well as
PCI_TRDY, PCI_STOP, and PCI_PERR) for one clock cycle to allow the other target to stop driving the
bus.
16.4.2.10 Dual Address Cycles
The PCI controller supports dual address cycle (DAC) commands (64-bit addressing on PCI bus) as both
an initiator and a target. DACs are different from single address cycles (SACs) in that the address phase
takes two PCI beats instead of one PCI beat to transfer (64-bit vs. 32-bit addressing). Only PCI memory
commands can use DAC cycles; I/O, configuration, interrupt acknowledge, and special cycle command
cannot use DAC cycles. The PCI controller block supports single-beat and burst DAC transactions.
For the case of the local processor, DAC generation depends on the setting of the POTEARx. If the
POTEARx are programmed with nonzero values and a transaction from the local processor core hits in
one of the outbound windows, a DAC transaction is generated on the PCI bus with the translated lower
32-bit addresses. Refer to
Section 16.3.1.2, “PCI ATMU Outbound Registers,”
for more information.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
16-56
Freescale Semiconductor