MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1260

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SATA Controller
Table 19-27
Table 19-28
Table 19-29
Table 19-30
19-30
31–12
31–2
Bit
1–0
11
10
Bit
31–22
21–16
9
8
7
6
31–2
6–2
1–0
1–0
Bit
Bit
7
Name
Name
—
—
Q
V
C
R
B
TTL
—
shows word 0—data base address—of the command header.
shows word 1—FIS_LEN—of the command header.
shows word 2—data base address—of the command header.
shows word 3—description information—of the command header.
PRD_ENTRY
FIS_LEN
Name
Reserved
Reserved, should be 1.
Vendor BIST. When this bit is set, it indicates that the command is a Vendor BIST, thus FIS will loop back at
the PHY local test.
Snoop enable during all descriptor read/write operations associated with this command.
Queued. Command is an FPDMA queued command.
Reset. The command is a SRST or device reset.
BIST. The command will require the host to enter BIST mode.
CDA
Name
—
Total transfer length. This is a 30-bit word count of the total length of the data transfer. It is used to detect
overruns/underruns between the transfer lengths programmed in the command and the PRDT.
Reserved
—
—
—
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Command descriptor base address. Indicates the 32-bit physical address of the command
descriptor block. The block must be word-aligned, indicated by bits 1–0 being reserved.
Reserved
Reserved
Number of PRD entries including indexed entries.
Reserved
FIS length. This is a 5-bit word count of the total length of the control or vendor-specific FIS
to transfer.
Reserved
Table 19-30. Word 3—Description Information
Table 19-27. Word 0—Data Base Address
Table 19-29. Word 2—Data Base Address
Table 19-28. Word 1—FIS_LEN
Description
Description
Description
Description
Freescale Semiconductor