MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 352

Manufacturer Part Number

BOARD DEV SYSTEM MPC8536E

Manufacturer

Freescale Semiconductor

PowerQUICC III™r

Board, Software and Documentation

Processor Series

Data Bus Width

Maximum Clock Frequency

Operating Supply Voltage

- 0.3 V to + 1.21 V

Maximum Operating Temperature

Data Ram Size

Interface Type

Program Memory Type

DDR2, DDR3, SDRAM

Program Memory Size

Digital Ic Case Style

Supply Voltage Range

0.95V To 1.05V

Rohs Compliant

For Use With/related Products

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

DDR Memory Controller

The DDR memory controller facilitates system design flexibility by providing a write timing adjustment

parameter, write data delay, (TIMING_CFG_2[WR_DATA_DELAY]) for data and DQS. The DDR

SDRAM specification requires DQS be received no sooner than 75% of an SDRAM clock period—and

no later than 125% of a clock period—from the capturing clock edge of the command/address at the

SDRAM. The WR_DATA_DELAY parameter may be used to meet this timing requirement for a variety

of system configurations, ranging from a system with one DIMM to a fully populated system with two

DIMMs. TIMING_CFG_2[WR_DATA_DELAY] specifies how much to delay the launching of DQS and

data from the first clock edge occurring one SDRAM clock cycle after the command is launched. The

delay increment step sizes are in 1/4 SDRAM clock periods starting with the default value of 0.

DDR SDRAM Write Timing Adjustments

shows the registered DDR SDRAM DIMM single-beat write timing.

MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1

Figure 8-54. Registered DDR SDRAM DIMM Burst Write Timing

Freescale Semiconductor