MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1280

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Secure Digital Host Controller
20.4.1
The DMA system address register contains the lower 32-bits of the system memory address used for DMA
transfers. Only access this register when no transactions are executing (after transactions have stopped).
The host driver should wait until PRSSTAT[DLA] is cleared.
20.4.2
The block attributes register configures the number of data blocks and the number of bytes in each block.
Only access this register when no transactions are executing (after transactions have stopped). The host
driver should wait until PRSSTAT[DLA] is cleared. During a data transfer,
20-6
DS_ADDR
Reset
Offset: 0x000
Offset: 0x004 (BLKATTR)
Reset 0
Field
•
•
0–31
W
W
R
R
Reading this register may return an invalid value.
Writing this register is ignored.
0
0
0
DMA System Address Register (DSADDR)
Block Attributes Register (BLKATTR)
DMA system address, lower 32 bits. When the eSDHC stops a DMA transfer, this register points to the system
address of the next contiguous data position. The upper four bits of the DMA system address are stored in
ECMCR[ESDHC_UPRADR], see
Note: The DS_ADDR must be aligned to a four-byte boundary; the two least-significant bits must be cleared.
0
0
This register contains only the lower 32 bits of the DMA address. The 4
high-order bits are in ECMCR[ESDHC_UPRADR]; see
“ECM Control Register
0
0
0
0
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
0
0
0
0
Figure 20-3. DMA System Address Register (DSADDR)
0
0
Figure 20-4. Block Attributes Register (BLKATTR)
BLKCNT
0
0
Table 20-3. DSADDR Field Descriptions
0
0
0
0
(ECMCR),” for this register.
0
0
Section 23.4.1.26, “ECM Control Register
0
0
0
0
0
0
NOTE
0
0
DS_ADDR
Description
15 16
0
0
0
0
—
0
0
18 19
0
0
0
0
0
0
Section 23.4.1.26,
0
0
(ECMCR)”.
0
0
0
0
0
BLKSZE
0
Freescale Semiconductor
0
0
0
0
Access: Read/Write
Access: Read/Write
0
0
1
1
0
0
0
0
31
31
0
0