MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 292

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DDR Memory Controller
Table 8-10
8-18
12–15
16–19
9–11
Bits
0–1
2–3
4–5
6–7
8
ACT_PD_EXIT Active powerdown exit timing (t
PRE_PD_EXIT Precharge powerdown exit timing (t
describes TIMING_CFG_0 fields.
Name
WWT
RWT
WRT
RRT
—
—
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Read-to-write turnaround (t
turnaround. If 0 clocks is chosen, then the DDR controller uses a fixed number based on the CAS
latency and write latency. Choosing a value other than 0 adds extra cycles past this default
calculation. As a default the DDR controller determines the read-to-write turnaround as CL – WL +
BL/2 + 2. In this equation, CL is the CAS latency rounded up to the next integer, WL is the
programmed write latency, and BL is the burst length.
00 0 clocks
01 1 clock
Write-to-read turnaround. Specifies how many extra cycles are added between a write to read
turnaround. If 0 clocks is chosen, then the DDR controller uses a fixed number based on the, read
latency, and write latency. Choosing a value other than 0 adds extra cycles past this default
calculation. As a default, the DDR controller determines the write-to-read turnaround as WL – CL +
BL/2 + 1. In this equation, CL is the CAS latency rounded down to the next integer, WL is the
programmed write latency, and BL is the burst length.
00 0 clocks
01 1 clock
Read-to-read turnaround. Specifies how many extra cycles are added between reads to different
chip selects. As a default, 3 cycles are required between read commands to different chip selects.
Extra cycles may be added with this field. Note: If 8-beat bursts are enabled, then 5 cycles are the
default. Note that DDR2 does not support 8-beat bursts.
00 0 clocks
01 1 clock
Write-to-write turnaround. Specifies how many extra cycles are added between writes to different
chip selects. As a default, 2 cycles are required between write commands to different chip selects.
Extra cycles may be added with this field. Note: If 8-beat bursts are enabled, then 4 cycles are the
default. Note that DDR2 does not support 8-beat bursts.
00 0 clocks
01 1 clock
Reserved, should be cleared.
exiting active powerdown before issuing any command.
000
001
010
011
precharge powerdown before issuing any command.
0000 Reserved
0001 1 clock
0010 2 clocks
0011 3 clocks
0100 4 clocks
0101 5 clocks
0110 6 clocks
0111 7 clocks
Reserved, should be cleared.
Reserved
1 clock
2 clocks
3 clocks
Table 8-10. TIMING_CFG_0 Field Descriptions
RTW
). Specifies how many extra cycles are added between a read to write
XARD
XP
and t
). Specifies how many clock cycles to wait after exiting
XARDS
Description
). Specifies how many clock cycles to wait after
10 2 clocks
11 3 clocks
10 2 clocks
11 3 clocks
10 2 clocks
11 3 clocks
10 2 clocks
11 3 clocks
100
101
110
111
1000 8 clocks
1001 9 clocks
1010 10 clocks
1011 11 clocks
1100 12 clocks
1101 13 clocks
1110 14 clocks
1111 15 clocks
4 clocks
5 clocks
6 clocks
7 clocks
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