MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1596

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Debug Features and Watchpoint Facility
Table 25-11
The following table,
different interfaces supported by the watchpoint monitor.
25-14
13–15 Reserved
20–24 Reserved
26–31 Reserved
Bit
10
11
12
16
17
18
19
25
0–31
Bits
0
1
2
3
4
5
6
7
8
9
Write with local processor snoop
Write with no local processor snoop
Write with allocate(L2 stashing)
Write with allocate and lock (L2 stashing with locking) Write with allocate and lock
Reserved
Reserved
Reserved
Reserved
Read with local processor snoop
Read with no local processor snoop
Read with unlock
Reserved
Reserved
ATOMIC clear
ATOMIC set
ATOMIC decrement
ATOMIC increment
Address only transaction
WMTM Watchpoint monitor transaction mask. Each bit corresponds to a transaction type as defined in
Name
describes the WMTMR fields.
e500 Coherency Module Dispatch
The transaction associated with any particular bit may be different depending on the interface being
monitored. A value of 1 for a given mask bit enables the matching of the transaction associated with that
bit. These bits are meaningful only when WMCR0[TMD]=0.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table
25-12, defines the transactions associated with each transaction mask bit for the
Table 25-12. Transaction Types By Interface
Table 25-11. WMTMR Field Descriptions
Description
ATOMIC decrement
ATOMIC increment
Write with allocate
Description
Read with unlock
DDR Controller
ATOMIC clear
ATOMIC set
Write
Read
—
—
—
—
—
—
—
—
—
—
—
—
PCI Outbound
Memory Read
Memory write
I/O Read
Request
I/O write
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Freescale Semiconductor
Non-posted Write
Read Response
PCI Express
Posted Write
Transaction
Outbound
Table
Read
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
25-12.