MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 457

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

There are two kinds of link table entries: “regular” entries or “next” entries (which have the N bit cleared
or set, respectively). Each “regular” entry specifies a memory segment by means of a 36-bit starting
address (SEGPTR) and a 16-bit length (SEGLEN). A “next” entry is used at the end of a link table to
specify that the list of memory segments is continued in another link table. In a “next” entry, the N bit is
set, the SEGPTR field gives the address of the next link table, and the SEGLEN field must be cleared. A
chain of link tables may contain any number of link tables. Whether the list of memory segments is in a
single link table or split into several link tables, the last entry in the last link table is a “regular” entry with
the R (return) bit set. The R bit signifies the end of link table operations so that the channel returns to the
descriptor for its next pointer (if any).
Freescale Semiconductor
16-21
24-27
28-31
32-63
Bits
0-15
22
23
SEGPTR
SEGLEN
Name
EPTR
—
—
R
N
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Length: 0-15
When N=0, SEGLEN is in the range 1 to 65535, specifying the number of bytes in the memory
segment pointed to by SEGPTR. A value of 0 causes the SGZL error bit to be set in the
Channel Status (see
When N=1, SEGLEN must be 0.
Reserved
Return:
When N=0:
0 No special action.
1 Indicates the last entry in the chain of link tables. If this entry does not specify the right
number of bytes to complete the last parcel, a G-STATE or S-STATE error is set in the Channel
Status Register (see
When N=1, ignored.
Next:
0 No special action.
1 Indicates the last dword in the current link table. The SEGPTR field is the address of the
next link table in the chain.
Reserved
Extended Pointer: Concatenated as the top 4 bits of the segment pointer when EAE is high
(see the EAE bit in
Segment pointer: A memory address.
Table 10-9. Link Table Field Definitions
Table
Section 10.4.4.2, “Channel Status Register
Section 10.4.4.2, “Channel Status Register
10-11).
Description
(CSR)”).
(CSR)”).
Security Engine (SEC) 3.0
10-27