MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 607

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

11.4.1.6
Address compare block determines if a slave has been properly addressed, either by its slave address or by
the general broadcast address (which addresses all slaves). The three performed address comparisons are
described as follows:
11.4.2
The I
on it. If two or more masters simultaneously try to control the bus, each master’s clock synchronization
procedure (including the I
clock low period and the high is equal to the shortest one among the masters. A bus master loses arbitration
if it transmits a logic 1 on SDA while another master transmits a logic 0. The losing masters immediately
switch to slave-receive mode and stop driving the SDA line. In this case, the transition from master to slave
mode does not generate a STOP condition. Meanwhile, the I
indicate the loss of arbitration and, as a slave, services the transaction if it is directed to itself.
If the I
11.4.2.1
The arbitration control block controls the arbitration procedure of the master mode. A loss of arbitration
occurs whenever the master detects a 0 on the external SDA line while attempting to drive a 1, tries to
generate a START or restart at an inappropriate time, or detects an unexpected STOP request on the line.
In master mode, arbitration by the master is lost (and I2CSR[MAL] is set) under the following conditions:
Note that the I
Freescale Semiconductor
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C interface is a true multiple-master bus that allows more than one master device to be connected
2
— Ack cycle
Whether a broadcast message has been received, to update the I2CSR
Whether the module has been addressed as a slave, to update the I2CSR and to generate an interrupt
If the address transmitted by the current master matches the general broadcast address
Slave mode—The I
a subsequent START condition is detected.
Master mode—The I
condition is initiated, the current bus cycle can be corrupted. This ultimately results in the current
bus master of the I
SDA samples low when the master drives high during an address or data-transmit cycle (transmit).
SDA samples low when the master drives high during a data-receive cycle of the acknowledge
(Ack) bit (receive).
A START condition is attempted when the bus is busy.
A repeated START condition is requested in slave mode.
A start condition is attempted when the requesting device is not the bus owner
Unexpected STOP condition detected
C module is enabled in the middle of an ongoing byte transfer, the interface behaves as follows:
Arbitration Procedure
Address Compare—Implementation Details
Arbitration Control
2
C module does not automatically retry a failed transfer attempt.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
2
2
2
C module) determines the bus clock—the low period is equal to the longest
C interface losing arbitration, after which bus operations return to normal.
C module ignores the current transfer on the bus and starts operating whenever
2
C module cannot tell whether the bus is busy; therefore, if a START
2
C unit sets the I2CSR[MAL] status bit to
I
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C Interfaces
11-15