MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1394

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Universal Serial Bus Interfaces
21.5.7
The periodic frame span traversal node (FSTN) data structure is to be used only for managing full- and
low-speed transactions that span a host-frame boundary. Software must not use an FSTN in the
asynchronous schedule. An FSTN in the asynchronous schedule results in undefined behavior. Software
must not use the FSTN feature with a host controller whose HCIVERSION register indicates a revision
implementation under 0x0096. Note that FSTNs were not defined for EHCI implementations before
Revision 0.96 of the EHCI Specification and their use may yield undefined results.
21-60
DWord
31
5
6
6
6
6
8
9
9
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Offset
0x14
0x18
0x18
0x18
0x18
0x20
0x24
0x24
QH
Periodic Frame Span Traversal Node (FSTN)
Table 21-59. Host-Controller Rules for Bits in Overlay (DWords 5, 6, 8, and 9)
11–10
11–5
Bits
4–1
7–0
4–0
31
15
0
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
C-prog-mask
FrameTag
Status[0]
NakCnt
S-bytes
Figure 21-41. Frame Span Traversal Node Structure
Name
Cerr
ioc
dt
Normal Path Link Pointer
Back Path Link Pointer
Nak counter—RW. This field is a counter the host controller decrements
whenever a transaction for the endpoint associated with this queue head results
in a Nak or Nyet response. This counter is reloaded from RL before a transaction
is executed during the first pass of the reclamation list (relative to an
Asynchronous List Restart condition). It is also loaded from RL during an overlay.
Data toggle. The Data toggle control controls whether the host controller
preserves this bit when an overlay operation is performed.
Interrupt on complete. The ioc control bit is always inherited from the source qTD
when the overlay operation is performed.
Error counter. Copied from the qTD during the overlay and written back during
queue advancement.
Ping state (P)/ERR. If the EPS field indicates a high-speed endpoint, then this
field should be preserved during the overlay operation.
Split-transaction complete-split progress. Initialized to zero during any overlay.
This field is used to track the progress of an interrupt split-transaction.
Software must ensure that the S-bytes field in a qTD is zero before activating the
qTD. Keeps track of the number of bytes sent or received during an IN or OUT
split transaction.
Split-transaction frame tag. Initialized to zero during any overlay. This field is used
to track the progress of an interrupt split-transaction.
15
14 13 12 11 10
Description
9
8
7
6
5
Freescale Semiconductor
4
00
00
3
2
Typ
Typ
1
T 0x00
T 0x04
0
Offset