MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1559

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

In addition to these registers, the interrupt control provides four pairs of mask registers that can be used to
monitor message, interprocessor, timer, and external interrupts. See
Mask Registers (PMMRs),” on page
24.3.2
This section describes the performance monitor control registers in detail.
24.3.2.1
The performance monitor global control register (PMGC0), shown in
to control all PMCs.
Table 24-2
Freescale Semiconductor
Address Offset
Offset 0xE_1000
Reset
0xE_10A4
0xE_10A8
(in Hex)
3–31
Bits
0
1
2
W
R
FAC PMIE FCECE
(DISCOUNT)
0
describes PMGC0 fields.
Control Registers
FCECE
Name
PMIE
Performance Monitor Global Control Register (PMGC0)
FAC
—
1
PMLCB9—Performance monitor local control register B9
PMC9—Performance monitor counter 9
Figure 24-2. Performance Monitor Global Control Register (PMGC0)
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
2
Freeze all counters.
0 PMCs are incremented (if permitted by other PMGC0/PMLC bits).
1 PMCs are not incremented. Set by hardware when an interrupt is signalled and FCECE =1.
Performance monitor interrupt enable. Interrupts are caused by PMC overflows.
0 Interrupts are disabled.
1 Interrupts are enabled and occur when an enabled condition or event occurs.
Freeze counters on enabled condition or event. An enabled condition or event is defined as:
The use of the trigger and freeze counter conditions depends on the enabled condition.
0 PMCs can be incremented (if permitted by other control bits).
1 PMCs can be incremented (if permitted by other control bits) only until an enabled condition
Reserved
or event occurs, at which time PMGC0[FAC] is set. It is up to software to clear FAC.
Table 24-1. Control Register Memory Map (continued)
3
The msb = 1 in PMC n and PMLCA n [CE] = 1.
Table 24-2. PMGC0 Field Descriptions
9-32.
Register
All zeros
Description
—
Section 9.3.4, “Performance Monitor
Figure
Access
R/W
R/W
24-2, is a 32-bit register used
0x0000_0000
0x0000_0000
Reset
Device Performance Monitor
Access: Read/Write
24.3.3.1/24-10
Section/Page
24.3.2.2/24-6
24-5
31