MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 197

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.5
4.5.1
Selecting on-chip ROM in boot ROM location, see
on-chip ROM. The on-chip ROM is selected by configuring the POR config pins cfg_rom_loc[0:3]. Two
different configurations are provided for boot from the on-chip ROM - boot from eSPI and from eSDHC.
4.5.1.1
4.5.1.1.1
The MPC8536E is capable of loading initialization code from a memory device that is connected to the
eSDHC controller interface. This device can be either a SD or MMC card or other variants compatible with
these devices. The term SD/MMC will be used when referring to the memory device.
Boot from eSDHC is supported by the MPC8536E using an on-chip ROM which contains the basic
eSDHC device driver and the code to perform block copy from SD/MMC to any target memory. Selecting
on-chip ROM in boot ROM location (see
ROM. The on-chip ROM is selected by configuring the POR config pins cfg_rom_loc[0:3]. Prior to boot,
the user must ensure that the SD/MMC card to boot from is inserted.
Freescale Semiconductor
Note: The logic circuits shown depict functional relationships only; they do not represent physical implementation details.
Fixed-interval timer events based on one of the
Watchdog timer events based on one of the
Book E–defined TCR[WP] (WPEXT||WP).
Initialization/Applications Information
32
64 TB bits selected by the EIS-defined
Book E–defined TCR[FP] (FP||FPEXT).
Decrementer Event
e500 Core
64 TB bits selected by the EIS-defined
System Boot
TCR[WPEXT] concatenated with the
(0 ⇒ 1 Detect)
eSDHC Boot
TCR[FPEXT] concatenated with the
Overview
TBU
Core Time Base (Incrementer)
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Figure 4-7. RTC and Core Timer Facilities Clocking Options
63
32
(Decrementer)
32
DECAR
Table
TBL
DEC
Auto-Reload
4-14) causes the e500 CPU to fetch data from the on-chip
HID0
Table
63
63
4-14, causes the e500 CPU to fetch data from the
Core Timer
Facilities Clock
TBEN
8
SEL_TBCLK
Reset, Clocking, and Initialization
RTC
(Sampled
CCB
Clock
4-27