MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1668

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Revision History
14.5.3.1.8, 14-39
14.5.3.2.1, 14-42
14.5.3.5.1, 14-74
14.5.3.5.2, 14-76
14.5.3.5.5, 14-79
14.5.3.6, 14-87
14.5.3.6.25, 14-99
14.5.3.6.41, 14-107
B-4
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Corrected DMACTRL[TOD] field definition by replacing the “1” definition with
the following:
1
Changed TCTRL[TXSCHED] field description for 01 state to read as follows:
01
in ascending ring index order.
Added the following note to descriptions of MACCFG1 fields Tx_Flow and
Rx_Flow:
Note: Should not be set when operating in Half-Duplex mode
In MACCFG2[Huge Frame] field description, updated the right-hand “Buffer
descriptor updated” column as follows:
Replaced first paragraph of field description of Maximum Frame with the
following:
This field is set to 0x0600 (1536 bytes) by default and always must be set to a
value greater than or equal to 0x0040 (64 bytes), but not greater than 0x2580
(9600 bytes). It sets the maximum Ethernet frame size in both the transmit and
receive directions. (Refer to MACCFG2[Huge Frame].) It does not affect the size
of packets sent or received via the FIFO packet interface.
Added note to end of section:
The transmit and receive frame counters (TR64, TR127, TR 255, TR511, TR1K,
TRMAX, adn TRMGV) do not increment for aborted frames (collision retry limit
exceeded, late collision, underrurn, EBERR, TxFIFO data error, frame truncated
due to exceeding MAXFRM, or excessive deferral).
Replaced second sentence of TBYT[TBYT] with the following:
This count does not include preamble/SFD or jam bytes, except for half-duplex
flow control (back-pressure triggered by TCTRL[THDF]=1). For THDF, the sum
total of ‘phantom’ preamble bytes transmitted for flow control purposes is
included in the TBYT increment value of the next frame to be transmitted, up to
65,535 bytes of frame and phantom preamble.
Replaced description of TOVR[TOVR] with the following:
Transmit oversize frame counter. Increments each time a frame is transmitted
which exceeds 1518 (non VLAN) or 1522 (VLAN) with a correct FCS value.
Receive or transmit
Receive
Transmit
Receive or transmit
eTSEC immediately fetches a new TxBD from ring 0.
Priority scheduling mode. Frames from enabled TxBD rings are serviced
Frame type
...
...
...
...
...
Buffer descriptor
updated
yes
yes
no
no
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