MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1543

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

When waking from Deep Sleep if GCR[DEEPSLEEP_Z]=1, pad inputs are re-enabled as soon as the
wakeup event occurs, but pad outputs are un-tristated only after the reset counter PMRCCR[RCNT]
expires.
23.5.1.6.5
Jog mode provides a dynamic mechanism to lower (or raise) the CPU core clock while leaving the platform
clock rate unchanged ( for example, to optimize Tj (junction temperature) and power dissipation of the
device). In doing this, the timing of an application at lower clock rate would behave lethargically, but all
tasks and system timing would be maintained.
The term jog mode arose because it can be a slower version of run; however, despite the name of the mode,
there is no requirement that it be used to slow down the core; it could equally be used to speed up the core
(providing that the new core frequency is still within the frequency specifications of the MPC8536E). Jog
mode does not impact static (leakage) power.
Before initiating jog mode, it is the user’s software responsibility to save state of the device as required.
(The core is reset, but not the platform.) The user’s software must also configure the boot vector for the
warm reset boot code as appropriate (similar to what is done for deep sleep mode). This typically involves
modifying the boot page translation register (BPTR) and/or local access windows as required.
Peripherals in the platform need not be disabled by software; however, because they will not be operating
during the jog mode frequency transition process it is possible that I/O peripherals such as PCI and eTSEC
may lose packets during the jog mode frequency transition. Therefore, in certain applications the user may
wish to disable the I/O peripherals manually before entering jog mode.
Note that as well as being used to define the new core frequency for a Jog Request, the
PMJCR[e500_Ratio] is also used as the new e500 ratio when waking from Deep Sleep.
When a jog mode request is initiated (by setting POWMGTCSR[JOG]), the following sequence of events
is performed:
Freescale Semiconductor
1. The system operates as if a request to enter Sleep mode has occured, with the exception that the
2. The system isolates the outputs of the core complex (e500 and L2), as per Deep Sleep mode.
3. Reset the core (warm reset) to initiate e500 boot. This is as per Deep Sleep mode. However, rather
4. As per an exit from Deep Sleep, when the e500 PLL regains lock the platform clocks are re-enabled
5. After a jog sequence as defined above, the new e500 clock ratio is reflected in
values written into the PMCDR register are ignored, and it is treated as if every bit in PMCDR is
a logic 1. This means that the eTSECs, USB controllers, DDR and eLBC will be stopped.
However, power is NOT removed from the core complex and the POWER_EN output pin is not
deasserted. Because power is NOT removed from the core complex, this also means that the inputs
of the core complex are not isolated (unlike Deep Sleep).
than setting the AUTORSTSR[rst_dpslp] bit, a different bit called AUTORSTSR[rst_jog] is set by
hardware.
and the system resumes operation.
PORPLLSR[e500_Ratio]. Therefore, after jog the values in PORPLLSR may not necessarily
reflect the values driven by the the POR config pins.
Jog Mode
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Global Utilities
23-51