MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 394

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Programmable Interrupt Controller (PIC)
9.3.2.1
The TFRRs, shown in
timers. Note that although TFRRs are read/write, the PIC ignores the register values.
Table 9-13
9.3.2.2
The GTCCRs, shown in
the two groups.
Table 9-14
9-24
0–31 FREQ Timer frequency (in ticks/second (Hz)). Used to communicate the frequency of the global timers’ clock source,
Bits Name
Offset Group A: GTCCRA0: 0x1100; GTCCRA1: 0x1140; GTCCRA2: 0x1180; GTCCRA3: 0x11C0
Reset
1–31 COUNT Current count. Decremented while GTBCR xn [CI] is zero. When the timer count reaches zero, an interrupt is
Bits
Offset TFRRA: 0x10F0; TFRRB: 0x20F0
Reset
0
W
R TOG
W
R
Group B: GTCCRB0: 0x2100; GTCCRB1: 0x2140; GTCCRB2: 0x2180; GTCCRB3: 0x21C0
Name
TOG
0
0
describes the TFRRx registers.
describes the GTCCRxn fields.
(either the CCB clock or the frequency of the RTC signal), to user software. TFRR x is set only by software for later
use by other applications and its value in no way affects the operating frequency of the global timers. The timers
operate at a ratio of this clock frequency, as set by TCR x [CLKR]. See
(TCRA–TCRB).”
1
Timer Frequency Reporting Register (TFRRA–TFRRB)
Global Timer Current Count Registers (GTCCRA0–GTCCRA3,
GTCCRB0–GTCCRB3)
Toggle. Toggles when the current count decrements to zero. Cleared when GTBCR xn [CI] goes from 1 to 0.
generated (provided it is not masked), the toggle bit is inverted, and the count is reloaded. For non-cascaded
timers, the reload value is the contents of the corresponding GTBCR xn . Cascaded timers are reloaded with
either all ones, or the GTBCR xn contents, depending on the value of TCR n [ROVR]. See
Control Registers
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Figure 9-12. Global Timer Current Count Registers (GTCCR xn )
Figure
Figure 9-11. Timer Frequency Reporting Registers (TFRR x )
Figure
(TCRA–TCRB),” for more details.
9-11, are written by software to report the clocking frequency of the PIC
9-12, contain the current count for each of the four PIC timers in each of
Table 9-14. GTCCR xn Field Descriptions
Table 9-13. TFRR x Field Descriptions
All zeros
All zeros
FREQ
Description
Description
COUNT
Section 9.3.2.6, “Timer Control Registers
Freescale Semiconductor
Section 9.3.2.6, “Timer
Access: Read/Write
Read only
Access:
31
31