MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1028

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PCI Bus Interface
16.1.1
The PCI controller connects the OCeaN to the PCI bus, to which I/O components are connected. The PCI
bus uses a 32-bit multiplexed address/data bus, plus various control and error signals. The PCI interface
supports address and data parity with error checking and reporting.
The integrated processor’s PCI interface functions both as a master (initiator) and a target device.
Internally, the design is divided into the following:
The data path blocks contain the queues, tables for transaction tracking, and ordering. The control blocks
contain control logic and state-machines for buffer control, bus protocol, tag generation, and transaction
resizing. The memory blocks are used solely for inbound and outbound data storage. This allows the
integrated processor to handle separate PCI transactions simultaneously. For example, consider the case
where a burst-write transaction from the integrated processor to another PCI device terminates with a
disconnect before finishing the transaction. If another PCI device is granted the PCI bus and requests a
burst-read from local memory, the integrated processor, as a target, can accept the burst-read transfer.
When the integrated processor is granted mastership of the PCI bus, the burst-write transaction continues.
The PCI interface does not flush pending outbound writes as a result of an inbound read command.
Systems must not rely on inbound reads to ensure all pending outbound writes have completed. For
16-2
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Data path blocks
Control logic blocks
Memory
Overview
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Figure 16-1. PCI Controller Block Diagram
OCeaN Physical Interface
PCI Bus Interface
OCeaN Gasket
PCI Interface
Regs
Arb
PCI
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