MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 817

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

reside in a different memory region (based at RBASEH).
RBDBPH register.
Table 14-38
14.5.3.3.11 Receive Buffer Descriptor Pointers 0–7 (RBPTR0–RBPTR7)
RBPTR0–RBPTR7 each contains the low-order 32 bits of the next receive buffer descriptor address for
their respective RxBD ring.
value of their ring’s associated RBASE when the RBASE register is written by software. Software must
not write RBPTRn while eTSEC is actively receiving frames. However, RBPTRn can be modified when
the receiver is disabled or when no Rx buffer is in use (after a GRACEFUL STOP RECEIVE command is
issued and the frame completes its reception) in order to change the next RxBD eTSEC receives.
Table 14-24
Freescale Semiconductor
28–31
29–31
0–27
0–28
Bits
Bits
Offset eTSEC1:0x2_4384+8 n ;
Offset eTSEC1:0x2_4380;
Reset
Reset
W
W
R
R
RBDBPH Most significant bits common to all data buffer addresses contained in RxBDs. The user must initialize
eTSEC3:0x2_6384+8 n
eTSEC3:0x2_6380
RBPTR n
0
0
Name
Name
—
—
describes the fields of the RBDBPH register.
describes the fields of the RBPTRn register.
Reserved
RBDBPH before enabling the eTSEC receive function.
Current RxBD pointer for RxBD ring n . Points to the current BD being processed or to the next BD the
receiver uses when it is idling. After reset or when the end of the RxBD ring is reached,
eTSEC initializes RBPTR n to the value in the corresponding RBASE n . The RBPTR register is internally
written by the eTSEC’s DMA controller during reception. The pointer increments by 8 (bytes) each time a
descriptor is closed successfully by the eTSEC. Note that the 3 least-significant bits of this register are
read only and zero.
Reserved
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Figure 14-35. RBPTR0–RBPTR7 Register Definition
Figure 14-35
Figure 14-34. RBDBPH Register Definition
Table 14-38. RBDBPH Field Descriptions
Table 14-39. RBPTR n Field Descriptions
describes the RBPTR registers. These registers takes on the
RBPTR n
—
All zeros
All zeros
Description
Description
Figure 14-34
Enhanced Three-Speed Ethernet Controllers
describes the definition for the
Access: Read/Write
Access: Read/Write
27 28
28 29
RBDBPH
—
14-69
31
31