MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 223

Manufacturer Part Number

BOARD DEV SYSTEM MPC8536E

Manufacturer

Freescale Semiconductor

PowerQUICC III™r

Board, Software and Documentation

Processor Series

Data Bus Width

Maximum Clock Frequency

Operating Supply Voltage

- 0.3 V to + 1.21 V

Maximum Operating Temperature

Data Ram Size

Interface Type

Program Memory Type

DDR2, DDR3, SDRAM

Program Memory Size

Digital Ic Case Style

Supply Voltage Range

0.95V To 1.05V

Rohs Compliant

For Use With/related Products

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

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SRAM features include the following:

Freescale Semiconductor

Error injection modes supported for testing error handling

SRAM regions are created by configuring 1, 2, 4 or 8 ways of each set to be reserved for

memory-mapped SRAM.

Regions can reside at any location in the memory map aligned to the SRAM size.

SRAM memory is byte addressable; for accesses of less than a cache line, ECC is updated using

read-modify-write transactions.

I/O devices access SRAM regions by marking transactions as snoopable (global).

lists the possible L2 cache/SRAM configurations.

512 Kbytes (8 ways)

448 Kbytes (7 ways)

384 Kbytes (6 ways)

320 Kbytes (5 ways)

256 Kbytes (4 ways)

192 Kbytes (3 ways)

128 Kbytes (2 ways)

MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1

Table 6-1. Available L2 Cache/SRAM Configurations

Stash-only Region

SRAM Region 1

SRAM Region 2

L2 Look-Aside Cache/SRAM

MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 223

MPC8536DS

Specifications of MPC8536DS

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