MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 98

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

4.3.6.5 Synthesizer Lock (SLOCK)
4.3.6.6 Reset Enable (RSTEN)
4.3.6.7 Low Power Stop Mode SCIM2 Clock (STSCIM)
4.3.6.8 Low Power Stop Mode External Clock (STEXT)
4.3.7 Clock Circuits Operation
4.3.7.1 Synthesizer Circuit
4.3.7.2 Phase Comparator and Filter
MC68F375
REFERENCE MANUAL
This read only status bit gives an indication of when the PLL is locked in at the speci-
fied frequency. Synthesizer lock occurs when the filter circuit switches from the wide
bandwidth to the narrow bandwidth mode (see
Filter).
SLOCK=0 is an indication that the PLL is enabled and is not yet locked into the narrow
bandwidth mode. If SLOCK=1, it indicates that either the PLL is disabled (system clock
is driven in directly), or the PLL is locked. This bit is used by the power on reset circuit
to determine whether the clock is stable or not.
This bit dictates what action to take when the loss of clock logic detects a loss of sys-
tem clock. If RSTEN=1, a loss of clock will cause a system reset. After completing a
normal reset sequence, the part will exit reset and run normally in limp mode. If
RSTEN is set while the MC68F375 is currently in limp mode, it will enter reset imme-
diately. If RSTEN=0, when a loss of clock occurs, the part will continue to run normally
in limp mode. This bit is cleared to 0 by reset.
This bit determines what happens to the SCIM2 clock when the CPU executes the
LPSTOP instruction. When STSCIM=0, the SCIM2 clock comes from the crystal oscil-
lator circuit and the VCO is turned off to save power. When STSCIM=1, the SCIM2
clock is driven from the VCO. STSCIM is cleared to 0 by reset.
This bit determines what happens to the external clock pin when the CPU executes
the LPSTOP instruction. When STEXT=0, no external clock will be driven in LPSTOP
mode. When STEXT=1, the external clock is driven from the SCIM2 clock as governed
by the STSCIM bit. STEXT is cleared to 0 by reset.
For the following discussion, refer to
The clocks for the MCU can be derived from an external crystal reference frequency
which is multiplied using the phase locked loop, frequency synthesizer circuit as
described below.
The output of the crystal oscillator is compared with the output of the divider chain to
determine the frequency relationship of the two signals. The result of this compare is
then filtered and used to control the voltage controlled oscillator (VCO).
SINGLE-CHIP INTEGRATION MODULE 2 (SCIM2E)
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
Rev. 25 June 03
Figure
4-2,
Figure
4.3.7.2 Phase Comparator and
4-3, and
Figure
4-4.
MOTOROLA
4-16