MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 342

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

8.2 TPU3 Components
8.2.1 Time Bases
8.2.2 Timer Channels
8.2.3 Scheduler
8.2.4 Microengine
MC68F375
REFERENCE MANUAL
The microcode ROM TPU3 functions that are available in the MC68F375 are
described in
The TPU3 consists of two 16-bit time bases, 16 independent timer channels, a task
scheduler, a microengine, and a host interface. In addition, a dual-ported parameter
RAM is used to pass parameters between the module and the CPU.
Two 16-bit counters provide reference time bases for all output compare and input
capture events. Prescalers for both time bases are controlled by the CPU via bit fields
in the TPU3 module configuration register (TPUMCR) and TPU module configuration
register two (TPUMCR2). Timer count registers TCR1 and TCR2 provide access to the
current counter values. TCR1 and TCR2 can be read by TPU microcode but are not
directly available to the CPU. The TCR1 clock is always derived from the system clock.
The TCR2 clock can be derived from the system clock or from an external input via
theT2CLK clock pin. The duration between active edges on the T2CLK clock pin must
be at least nine system clocks.
The TPU3 has 16 independent channels, each connected to an MCU pin. The chan-
nels have identical hardware and are functionally equivalent in operation. Each
channel consists of an event register and pin control logic. The event register contains
a 16-bit capture register, a 16-bit compare/match register, and a 16-bit greater-than-
or-equal-to comparator. The direction of each pin, either output or input, is determined
by the TPU microengine. Each channel can either use the same time base for match
and capture, or can use one time base for match and the other for capture.
When a service request is received, the scheduler determines which TPU3 channel is
serviced by the microengine. A channel can request service for one of four reasons:
for host service, for a link to another channel, for a match event, or for a capture event.
The host system assigns each active channel one of three priorities: high, middle, or
low. When multiple service requests are received simultaneously, a priority-scheduling
mechanism grants service based on channel number and assigned priority.
The microengine is composed of a control store and an execution unit. Control-store
ROM holds the microcode for each factory-masked time function. When assigned to a
channel by the scheduler, the execution unit executes microcode for a function
assigned to that channel by the CPU. Microcode can also be executed from the dual-
port RAM (DPTRAM) module instead of the control store. The DPTRAM allows emu-
lation and development of custom TPU microcode without the generation of a
microcode ROM mask. Refer to
APPENDIX D TPU ROM
Freescale Semiconductor, Inc.
For More Information On This Product,
TIME PROCESSOR UNIT 3
Go to: www.freescale.com
8.3.6 Emulation Support
Rev. 25 June 03
FUNCTIONS.
for more information.
MOTOROLA
8-2