MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 260

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

6.7.4.2 QSPI Interrupts
6.7.4.3 QSPI Flow
MC68F375
REFERENCE MANUAL
The QSPI has three possible interrupt sources but only one interrupt vector. These
sources are SPIF, MODF, and HALTA. When the CPU responds to a QSPI interrupt,
the user must ascertain the interrupt cause by reading the SPSR. Any interrupt that
was set may then be cleared by writing to SPSR with a zero in the bit position corre-
sponding to the interrupt source.
The SPIFIE bit in SPCR2 enables the QSPI to generate an interrupt request upon
assertion of the SPIF status flag. Because it is buffered, the value written to SPIFIE
applies only upon completion of the queue (the transfer of the entry indicated by
ENDPQ). Thus, if a single sequence of queue entries is to be transferred (i.e., no
WRAP), then SPIFIE should be set to the desired state before the first transfer.
If a sub-queue is to be used, the same CPU write that causes a branch to the sub-
queue may enable or disable the SPIF interrupt for the sub-queue. The primary queue
retains its own selected interrupt mode, either enabled or disabled.
The SPIF interrupt must be cleared by clearing SPIF. Subsequent interrupts may then
be prevented by clearing SPIFIE. Clearing SPIFIE does not immediately clear an inter-
rupt already caused by SPIF.
The QSPI operates in either master or slave mode. Master mode is used when the
MCU initiates data transfers. Slave mode is used when an external device initiates
transfers. Switching between these modes is controlled by MSTR in SPCR0. Before
entering either mode, appropriate QSMCM and QSPI registers must be initialized
properly.
In master mode, the QSPI executes a queue of commands defined by control bits in
each command RAM queue entry. Chip-select pins are activated, data is transmitted
from the transmit RAM and received by the receive RAM.
In slave mode, operation proceeds in response to SS pin assertion by an external SPI
bus master. Operation is similar to master mode, but no peripheral chip selects are
generated, and the number of bits transferred is controlled in a different manner. When
the QSPI is selected, it automatically executes the next queue transfer to exchange
data with the external device correctly.
Although the QSPI inherently supports multi-master operation, no special arbitration
mechanism is provided. A mode fault flag (MODF) indicates a request for SPI master
arbitration. System software must provide arbitration. Note that unlike previous SPI
systems, MSTR is not cleared by a mode fault being set nor are the QSPI pin output
drivers disabled. The QSPI and associated output drivers must be disabled by clearing
SPE in SPCR1.
Figure 6-4
ter and slave operation. The CPU must initialize the QSMCM global and pin registers
and the QSPI control registers before enabling the QSPI for either mode of operation.
The command queue must be written before the QSPI is enabled for master mode
shows QSPI initialization.
Freescale Semiconductor, Inc.
QUEUED SERIAL MULTI-CHANNEL MODULE
For More Information On This Product,
Go to: www.freescale.com
Rev. 25 June 03
Figure 6-5
through
Figure 6-9
show QSPI mas-
MOTOROLA
6-26