MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 129

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

MC68F375
REFERENCE MANUAL
Table 4-21
bus cycle terminations.
To control termination of a bus cycle for a retry or a bus error condition properly,
DSACK, BERR, and HALT must be asserted and negated with the rising edge of CLK-
OUT. This ensures that when two signals are asserted simultaneously, the required
setup time and hold time for both of them are met for the same falling edge of the MCU
clock. Refer to
ments. External circuitry that provides these signals must be designed with these
constraints in mind, or else the internal bus monitor must be used.
DSACK, BERR, and HALT may be negated after AS is negated.
Number
NOTES:
Case
1. N = The number of current even bus state (S2, S4, etc.).
2. A = Signal is asserted in this bus state.
3. NA = Signal is not asserted in this state.
4. X = Don’t care.
5. S = Signal was asserted in previous state and remains asserted in this state.
• Retry Termination
1
2
3
4
5
6
— HALT and BERR are asserted in lieu of, at the same time as, or before DSACK
or after DSACK (case 4), and HALT remains negated; BERR is negated at the
same time or after DSACK.
(case 5) or after DSACK (case 6); BERR is negated at the same time or after
DSACK; HALT may be negated at the same time or after BERR.
Control Signal
Table 4-21 DSACK, BERR, and HALT Assertion Results
shows various combinations of control signal sequences and the resulting
DSACK
DSACK
DSACK
DSACK
DSACK
DSACK
BERR
BERR
BERR
BERR
BERR
BERR
HALT
HALT
HALT
HALT
HALT
HALT
APPENDIX E ELECTRICAL CHARACTERISTICS
SINGLE-CHIP INTEGRATION MODULE 2 (SCIM2E)
Freescale Semiconductor, Inc.
For More Information On This Product,
Asserted on Rising
NA/A
NA/A
NA
A/S
A/S
Edge of State
NA
NA
NA
NA
NA
NA
N
A
A
A
A
A
A
A
2
1
3
Go to: www.freescale.com
Rev. 25 June 03
N + 2
NA
NA
NA
S
X
S
S
X
S
X
X
S
X
S
S
X
A
A
4
5
Normal termination.
Halt termination: normal cycle terminate and halt.
Continue when HALT is negated.
Bus error termination: terminate and take bus error
exception, possibly deferred.
Bus error termination: terminate and take bus error
exception, possibly deferred.
Retry termination: terminate and retry when HALT is
negated.
Retry termination: terminate and retry when HALT is
negated.
Result
for timing require-
MOTOROLA
4-47