MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 28

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

Freescale Semiconductor, Inc.
Page
Table
Number
Number
7-15 Transmit Pin Configuration ................................................................................ 7-27
7-16 CANCTRL1 Bit Settings..................................................................................... 7-28
7-17 PRESDIV Bit Settings....................................................................................... 7-29
7-18 CANCTRL2 Bit Settings.................................................................................... 7-29
7-19 TIMER Bit Settings ........................................................................................... 7-30
7-20 RXGMSKHI, RXGMSKLO Bit Settings ............................................................. 7-30
7-21 ESTAT Bit Settings ........................................................................................... 7-31
7-22 Transmit Bit Error Status ................................................................................... 7-32
7-23 Fault Confinement State Encoding .................................................................... 7-33
7-24 IMASK Bit Settings ........................................................................................... 7-33
7-25 IFLAG Bit Settings ............................................................................................ 7-33
7-26 RXECTR, TXECTR Bit Settings ....................................................................... 7-34
8-1 Enhanced TCR1 Prescaler Divide Values ............................................................ 8-6
8-2 TCR1 Prescaler Values ......................................................................................... 8-6
8-3 TCR2 Counter Clock Source ................................................................................. 8-7
8-4 TCR2 Prescaler Control......................................................................................... 8-8
8-5 TPU3 Register Map ............................................................................................... 8-9
8-6 TPUMCR Bit Settings ......................................................................................... 8-11
8-7 DSCR Bit Settings .............................................................................................. 8-12
8-8 DSSR Bit Settings............................................................................................... 8-13
8-9 TICR Bit Settings ................................................................................................ 8-14
8-10 CIER Bit Settings .............................................................................................. 8-14
8-11 CFSRx Bit Settings ........................................................................................... 8-15
8-12 HSQRx Bit Settings .......................................................................................... 8-16
8-13 HSSRx Bit Settings........................................................................................... 8-17
8-14 CPRx Bit Settings ............................................................................................. 8-17
8-15 Channel Priorities .............................................................................................. 8-17
8-16 CISR Bit Settings .............................................................................................. 8-18
8-17 TPUMCR2 Bit Settings ..................................................................................... 8-19
8-18 Entry Table Bank Location................................................................................. 8-19
8-19 System Clock Frequency/Minimum
Guaranteed Detected Pulse .......................................................................... 8-20
8-20 TPUMCR3 Bit Settings ..................................................................................... 8-20
8-21 Parameter RAM Address Map........................................................................... 8-21
9-1 DPTRAM Register Map ......................................................................................... 9-3
9-2 DPTMCR Bit Settings ........................................................................................... 9-4
9-3 DPTBAR Bit Settings ............................................................................................ 9-5
10-1 CMFI EEPROM Module External Signals.......................................................... 10-6
10-2 CMFI EEPROM Memory Map with 32-Bit Word ................................................ 10-7
10-3 CMFI Control Register Addressing .................................................................... 10-9
10-4 CMFIMCR Bit Settings.................................................................................... 10-10
10-5 CMFITST Bit Settings ...................................................................................... 10-13
10-6 CMF Programming Algorithm (v6 and Later)................................................... 10-13
MC68F375
LIST OF TABLES
MOTOROLA
REFERENCE MANUAL
Rev. 25 June 03
xxviii
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