MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 148

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

4.7.8.4 Fully (16-bit) Expanded Mode
MC68F375
REFERENCE MANUAL
NOTES:
Select Pin
DATA[7:3]
DATA10
DATA11
Like ADDR[2:0] (which can be disabled by setting the ABD bit in SCIMMCR), the R/W
line and instruction tracking pins (IPIPE/DSO and IFETCH/DSI) can be disabled by
setting RWD and CPUD bits in SCIMMCR, respectively.
Operation in 16-bit expanded mode is selected when BERR = 1 and DATA1 = 0 at the
release of RESET. In this configuration, ADDR[18:11]/PA[7:0] and ADDR[10:3]/
PB[7:0] become part of the address bus. Likewise, DATA[15:8]/PG[7:0] and
DATA[7:0]/PH[7:0] become the data bus. The ABD, RWD, and CPUD bits in SCIM-
MCR are clear, enabling ADDR[2:0], R/W, and the instruction tracking pins (IPIPE/
DSO and IFETCH/DSI), respectively. Ports A, B, G, and H are unavailable in 16-bit
expanded mode. The initial configuration of all other SCIM2E pins is controlled by
DATA[11:2] and DATA0 and is outlined in
1. The FASTREF function is used only at reset and serves no purpose during normal operation.
2. If DATA1 and DATA10 are low at the rising edge of RESET, the SCIM2E will operate in emulation mode, a special
3. For CSM to be active, the SCIM2E must be configured for emulation mode, as described above, and any on-chip
4. DATA11 must be high at the rising edge of RESET for normal MCU operation.
DATA0
DATA2
DATA8
DATA9
variation of 16-bit expanded mode.
masked ROM modules must be disabled by driving their associated data bus pins low at the rising edge of
RESET. At present, only masked ROM modules support memory emulation by means of the CSM chip select.
CSM will not assert on MCUs with flash EEPROM modules.
2
4
Table 4-27 Fully (16-bit) Expanded Mode Reset Configuration
ADDR[22:19]/CS[9:6]/PC[6:3]
External Bus Interface
ADDR23/CS10/ECLK
SINGLE-CHIP INTEGRATION MODULE 2 (SCIM2E)
IRQ[7:1]/PF[7:1]
Affected Pin(s)
Freescale Semiconductor, Inc.
FASTREF/PF0
FC0/CS3/PC0
FC2/CS5/PC2
DSACK0/PE0
DSACK1/PE1
BGACK/CSE
AVEC/PE2
RMC/PE3
SIZ0/PE6
SIZ1/PE7
CSBOOT
For More Information On This Product,
FC1/PC1
BG/CSM
BR/CS0
DS/PE4
AS/PE5
Go to: www.freescale.com
Rev. 25 June 03
Table 4-27
Default Function
Normal Operation
(Pin Held High)
16-bit CSBOOT
FASTREF
DSACK0
DSACK1
IRQ[7:1]
BGACK
AVEC
RMC
SIZ0
SIZ1
CS0
CS3
CS5
FC1
DS
BG
AS
below.
1
See
Table 4-28
Alternate Function
(Pin Held Low)
8-bit CSBOOT
Factory Test
PF[7:1]
CSM
CSE
FC0
FC1
FC2
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
PF0
BR
MOTOROLA
3
4-66