MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 404

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

MC68F375
REFERENCE MANUAL
State
S1
S2
S3
S4
S5
Normal array reads and register accesses
The Block protect information and pulse width tim-
ing control can be modified.
Normal read operation still occurs
The CMFI will accept the erase hardware interlock
write.
This write may be to any CMFI array location
Accesses to the registers are normal register ac-
cesses.
A write to CMFICTL2 cannot set EHV at this time
A write to the register is not an erase hardware in-
terlock write and the CMFI shall remain in state S2.
Erase margin reads will occur
Accesses to the registers are normal register ac-
cesses.
A write to CMFICTL2 can change EHV.
High voltage is applied to the array blocks to erase
the CMFI bit cells.
The pulse width timer is active if SCLKR[2:0]
and HVS can be polled to time the erase pulse
During erase the array will not respond to any ad-
dress.
Accesses to the registers are normal register ac-
cesses.
A write to CMFICTL2 can change EHV only.
These reads shall determine if the state of the bits
on the selected blocks needs further modification
by the erase operation.
Once a bit is fully erased it shall read as a 1.
All words within the blocks being erased must be
read to determine if erase is completed.
Erase Hardware Interlock Write:
Erase Margin Read Operation:
High voltage write enable
Table 10-16 Erase Interlock State Descriptions
Normal Operation:
Erase Operation:
Freescale Semiconductor, Inc.
Mode
CDR MoneT FLASH FOR THE IMB3 (CMFI)
For More Information On This Product,
Go to: www.freescale.com
Rev. 25 June 03
0
State
Next
S2
S1
S3
S1
S4
S1
S5
S4
S1
T2
T1
T3
T6
T4
T7
T5
T8
T9
Write to any CMFI array location is the
erase interlock write.
If the write is to a register the erase
hardware interlock write has not been
done and the CMFI shall remain in
state S2.
Write EHV = 0, write STOP = 1 or sys-
tem reset
Transition Requirement
Write SES = 0 or master reset
Write SES = 0 or master reset
Write SES = 0 or master reset
Write PE = 1, SES = 1
Hardware Interlock
Write EHV = 1
Write EHV = 1
Master reset
MOTOROLA
10-34