MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 369

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

9.5.4 Stop Operation
9.5.5 Freeze Operation
9.5.6 TPU3 Emulation Mode Operation
MC68F375
REFERENCE MANUAL
If a reset is generated by an asynchronous reset such as the loss of clocks or software
watchdog time-out, the contents of the RAM array are not guaranteed. (Refer to
Reset
status.)
Reset will also reconfigure some of the fields and bits in the DPTRAM control registers
to their default reset state. See the description of the control registers to determine the
effect of reset on these registers.
Setting the STOP control bit in the DPTMCR causes the module to enter its lowest
power-consuming state. The DPTMCR can still be written to allow the STOP control
bit to be cleared.
In stop mode, the DPTRAM array cannot be read or written. All data in the array is
retained. The BIU continues to operate to allow the CPU to access the STOP bit in the
DPTMCR. The system clock remains stopped until the STOP bit is cleared or the
DPTRAM module is reset.
The STOP bit is initialized to logical zero during reset. Only the STOP bit in the DPT-
MCR can be accessed while the STOP bit is asserted. Accesses to other DPTRAM
registers may result in unpredictable behavior. Note also that the STOP bit should be
set and cleared independently of the other control bits in this register to guarantee
proper operation. Changing the state of other bits while changing the state of the
STOP bit may result in unpredictable behavior.
The FREEZE line on the IMB3 has no effect on the DPTRAM module. When the freeze
line is set, the DPTRAM module will operate in its current mode of operation. If the
DPTRAM module is not disabled, (RAMDS = 0), it may be accessed via the IMB3. If
the DPTRAM array is being used by the TPU in emulation mode, the DPTRAM will still
be able to be accessed by the TPU microengine.
To emulate TPU3 time functions, the user stores the microinstructions required for all
time functions to be used, in the RAM array. This must be done with the DPTRAM in
its normal operating mode and accessible from the IMB3. After the time functions are
for a description of the MC68F375 reset sources, operation, control, and
A word (32-bit) write will be completed coherently only if the reset
occurs during the second (16-bit) write bus cycle. If reset occurs dur-
ing the first write bus cycle, only the first half word will be written to
the RAM array and the second write will not be allowed to occur. In
this case, the word data contained in the DPTRAM will not be coher-
ent. The first half word will contain the most significant half of the new
word information and the second half word will contain the least sig-
nificant half of the old word information.
Freescale Semiconductor, Inc.
For More Information On This Product,
DUAL-PORT TPU RAM (DPTRAM)
Go to: www.freescale.com
Rev. 25 June 03
NOTE
MOTOROLA
4.7
9-7