MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 462

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

MC68F375
REFERENCE MANUAL
Bit(s)
14:12
6:5
15
11
10
9
8
7
FORCA,
FORCB
IARB3
Name
IL[2:0]
FLAG
WOR
BSL
—
IN
Flag status. This status bit indicates whether or not an input capture or output compare event
has occurred. If the IL field is non-zero, an interrupt request is generated when the FLAG bit is
set. The flag clearing mechanism will work only if no flag setting event occurs between the read
and write operations; if a FLAG setting event occurs between the read and write operations, the
FLAG bit will not be cleared.
0 = An input capture or output compare event has not occurred.
1 = An input capture or output compare event has occurred.
Interrupt level. The three interrupt level bits are read/write control bits that select the priority level
of interrupt requests made by the DASM. These bits can be read or written at any time and are
cleared by reset.
000 = Interrupt disabled
001 = Interrupt level 1 (lowest)
010 = Interrupt level 2
011 = Interrupt level 3
100 = Interrupt level 4
101 = Interrupt level 5
110 = Interrupt level 6
111 = Interrupt level 7 (highest)
Interrupt arbitration bit 3. The read/write IARB3 bit works in conjunction with the IARB[2:0] field
in the BIUSM module configuration register. Each module that generates interrupt requests on
the IMB must have a unique value in the arbitration field (IARB). This interrupt arbitration iden-
tification number is used to arbitrate for the IMB when modules generate simultaneous interrupts
of the same priority.
Reserved
Wired-OR. In the DIS, IPWM, IPM and IC modes, the WOR bit is not used; reading this bit re-
turns the value that was previously written. In the OCB, OCAB and OPWM modes, the WOR bit
selects whether the output buffer is configured for open-drain or totem pole operation.
0 = Output buffer is totem pole.
1 = Output buffer is open-drain.
Bus select. This control bit selects the time base bus to be connected to the DASM.
0 = The DASM is connected to time base bus A.
1 = The DASM is connected to time base bus B.
Input pin status. In the DIS, IPWM, IPM and IC modes, this read-only status bit reflects the logic
level on the input pin. In the OCB, OCAB and OPWM modes, reading this bit returns the value
latched on the output flip-flop, after EDPOL polarity selection. Writing to this bit has no effect.
Force A, B. In the OCB, OCAB and OPWM modes, the FORCA, B bit allows the software to force
the output flip-flop to behave as if a successful comparison had occurred on channel A, B
(except that the FLAG bit is not set). Writing a one to FORCA, B sets the output flip-flop; writing
a zero to it has no effect. In the DIS, IPWM, IPM and IC modes, FORCA and FORCB are not
used and writing to them has no effect. Writing a one to both FORCA and FORCB simulta-
neously resets the output flip-flop
– In the DIS mode, the FLAG bit is cleared.
– In the IPWM mode, the FLAG bit is set each time there is a capture on channel A.
– In the IPM mode, the FLAG bit is set each time there is a capture on channel A, except
– In the IC mode, the FLAG bit is set each time there is a capture on channel A.
– In the OCB mode (i.e. when MODE0 = 0), the FLAG bit is only set each time there is a
– In the OPWM mode, the FLAG bit is set whenever there is a successful comparison on
for the first time.
successful comparison on channel B. In the OCAB mode (i.e. when MODE0 = 1), the
FLAG bit is set each time there is a successful comparison on either channel A or B.
channel A.
Freescale Semiconductor, Inc.
For More Information On This Product,
CONFIGURABLE TIMER MODULE (CTM9)
Table 13-11 DASMSIC Bit Settings
Go to: www.freescale.com
Rev. 25 June 03
Description
MOTOROLA
13-36