MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 281

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

6.8.4 SCI Status Register (SCxSR)
SCxSR — SCIx Status Register
MC68F375
REFERENCE MANUAL
RESET:
Bit(s)
MSB
15
1
0
0
SCxSR contains flags that show SCI operating conditions. These flags are cleared
either by SCIx hardware or by a read/write sequence. The sequence consists of read-
ing the SCxSR (either the upper byte, lower byte, or the entire half-word) with a flag bit
set, then reading (or writing, in the case of flags TDRE and TC) the SCxDR (either the
lower byte or the half-word).
The contents of the two 16-bit registers SCxSR and SCxDR appear as upper and
lower half-words, respectively, when the SCxSR is read into a 32-bit register. An upper
byte access of SCxSR is meaningful only for reads. Note that a word read can simul-
taneously access both registers SCxSR and SCxDR. This action clears the receive
status flag bits that were set at the time of the read, but does not clear the TDRE or
TC flags. To clear TC, the SCxSR read must be followed by a write to register SCxDR
(either the lower byte or the half-word). The TDRE flag in the status register is read-
only.
If an internal SCI signal for setting a status bit comes after the CPU has read the
asserted status bits but before the CPU has read or written the SCxDR, the newly set
status bit is not cleared. Instead, SCxSR must be read again with the bit set and
SCxDR must be read or written before the status bit is cleared.
14
0
Name
RWU
SBK
None of the status bits are cleared by reading a status bit while it is
set and then writing zero to that same bit. Instead, the procedure out-
lined above must be followed. Note further that reading either byte of
SCxSR causes all 16 bits to be accessed, and any status bits already
set in either byte are armed to clear on a subsequent read or write of
SCxDR.
13
0
RESERVED
Receiver wakeup. Refer to
0 = Normal receiver operation (received data recognized).
1 = Wakeup mode enabled (received data ignored until receiver is awakened).
Send break
0 = Normal operation.
1 = Break frame(s) transmitted after completion of current frame.
12
Table 6-24 SCCxR1 Bit Settings (Continued)
0
Freescale Semiconductor, Inc.
QUEUED SERIAL MULTI-CHANNEL MODULE
11
For More Information On This Product,
0
10
0
Go to: www.freescale.com
9
0
Rev. 25 June 03
6.8.7.8 Receiver
TDRE
8
1
NOTE
TC
7
1
Description
Wake-Up.
RDRF
6
0
RAF
5
0
0xYF FC0C, 0xYF FC24
IDLE
4
0
OR
3
0
NF
2
0
MOTOROLA
FE
1
0
LSB
6-47
PF
0
0