MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 103

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

MC68F375
REFERENCE MANUAL
When the CPU executes LPSTOP, a special CPU space bus cycle writes a copy of the
current interrupt mask into the clock control logic. The SCIM2E brings the MCU out of
low power stop mode when one of the following exceptions occur:
Refer to
more information.
During low power stop mode, unless the system clock signal is supplied by an external
source and that source is removed, the SCIM2E clock control logic and the SCIM2E
clock signal (SCIMCLK) continue to operate. The periodic interrupt timer and input
logic for the RESET and IRQ pins are clocked by SCIMCLK. The SCIM2E can also
continue to generate the CLKOUT signal while in low power stop mode.
During low power stop mode, the address bus and data bus continue to drive the
LPSTOP broadcast cycle, and bus control signals are negated. I/O pins configured as
outputs continue to hold their previous state; I/O pins configured as inputs will remain
in a high impedance state.
The STSCIM and STEXT bits in SYNCR determine clock operation during low power
stop mode.
The flow chart shown in
bits when the MCU enters low power stop mode. Any clock in the off state is held low.
If the synthesizer VCO is turned off during low power stop mode, PLL relock delay will
occur when the MCU exits LPSTOP mode and the VCO is re-enabled.
• RESET
• Trace
• SCIM2E interrupt of higher priority than the stored interrupt mask
4.4.9 Low Power Stop Mode
In LPSTOP mode, the crystal oscillator is not disabled and will con-
tinue to run.
SINGLE-CHIP INTEGRATION MODULE 2 (SCIM2E)
Freescale Semiconductor, Inc.
For More Information On This Product,
Figure 4-6
Go to: www.freescale.com
Rev. 25 June 03
summarizes the effects of the STSCIM and STEXT
and
NOTE
4.6.4.2 LPSTOP Broadcast Cycle
MOTOROLA
4-21
for