MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 569

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

MC68F375
REFERENCE MANUAL
Num
27A
29A
30A
39A
46A
47A
47B
20
21
22
23
24
25
26
27
28
29
30
31
33
35
37
39
46
48
53
54
55
56
57
70
71
72
Clock High to R/ W Low
R/ W Asserted to AS , CS Asserted
R/ W Low to DS , CS Asserted (Write)
Clock High to Data Out Valid
Data Out Valid to Negating Edge of AS , CS (Fast Write Cycle)
DS , CS Negated to Data Out Invalid (Data Out Hold)
Data Out Valid to DS , CS Asserted (Write)
Data In Valid to Clock Low (Data Setup)
Late BERR , HALT Asserted to Clock Low (Setup Time)
AS , DS Negated to DSACK[1] , BERR , HALT Negated
DS , CS Negated to Data In Invalid (Data In Hold)
DS , CS Negated to Data In High Impedance
CLKOUT Low to Data In Invalid (Fast Cycle Hold)
CLKOUT Low to Data In High Impedance
DSACK[1] Asserted to Data In Valid
Clock Low to BG Asserted/Negated
BR Asserted to BG Asserted
BGACK Asserted to BG Negated
BG Width Negated
BG Width Asserted
R/ W Width Asserted (Write or Read)
R/ W Width Asserted (Fast Write or Read Cycle)
Asynchronous Input Setup Time
Asynchronous Input Hold Time
DSACK[1] Asserted to BERR , HALT Asserted
Data Out Hold from Clock High
Clock High to Data Out High Impedance
R/ W Asserted to Data Bus Impedance Change
RESET Pulse Width (Reset Instruction)
BERR Negated to HALT Negated (Rerun)
Clock Low to Data Bus Driven (Show)
Data Setup Time to Clock Low (Show)
Data Hold from Clock Low (Show)
BR , BGACK , DSACK[1] , BERR , HALT
(V
DDH
= 5.0 Vdc
Freescale Semiconductor, Inc.
For More Information On This Product,
13
Table E-5 AC Timing (Continued)
10%, V
Characteristic
ELECTRICAL CHARACTERISTICS
12
DDL
Go to: www.freescale.com
and V
10
10
Rev. 25 June 03
,
14
11
DDSYN
10
10
= 3.3 Vdc
10%, V
SS
= 0 Vdc, T
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
DVASN
t
BRAGA
t
t
t
t
t
t
t
t
t
CLBAN
t
SCLDD
SCLDS
SCLDH
SNDOI
BELCL
t
t
t
HRPW
CHDO
t
SNDN
t
GAGN
t
RWAS
t
t
DOCH
CHDH
RADC
BNHN
CHRL
RAAA
RASA
DVSA
CLDH
DABA
DICL
SNDI
SHDI
CLDI
DADI
RWA
AIHT
t
t
AIST
GH
GA
A
= T
Min
0.25
0.25
0.25
0.25
0.25
512
L
35
10
75
45
20
—
—
—
—
—
—
—
0
3
0
0
1
1
1
1
3
8
0
0
0
8
5
to T
H
)
1
Max
0.5
0.5
0.5
0.5
0.5
MOTOROLA
—
—
—
—
—
—
—
40
—
28
—
45
25
—
—
—
—
—
—
—
—
14
—
—
—
—
—
2
Unit
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
cyc
cyc
ns
cyc
cyc
cyc
cyc
ns
ns
ns
ns
ns
cyc
ns
ns
cyc
cyc
cyc
cyc
cyc
ns
ns
ns
ns
cyc
ns
ns
ns
cyc
ns
cyc
ns
ns
E-7