MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 119

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

4.5.3 Operand Alignment
4.5.4 Misaligned Operands
4.5.5 Operand Transfer Cases
MC68F375
REFERENCE MANUAL
LONG WORD
THREE BYTE
WORD
BYTE
of a word-length operand are OP0 (most significant) and OP1. The single byte of a
byte-length operand is OP0.
The EBI data multiplexer establishes the necessary connections for different combina-
tions of address and data sizes. The multiplexer takes the two bytes of the 16-bit bus
and routes them to their required positions. Positioning of bytes is determined by the
SIZ[1:0] and ADDR0 outputs. SIZ1 and SIZ0 indicate the number of bytes remaining
to be transferred during the current bus cycle. The number of bytes transferred is equal
to or less than the size indicated by SIZ1 and SIZ0, depending on port width.
ADDR0 also affects the operation of the data multiplexer. During a bus transfer,
ADDR[23:1] indicate the word base address of the portion of the operand to be
accessed, and ADDR0 indicates the byte offset from the base.
The CPU32 uses a basic operand size of 16 bits. An operand is misaligned when it
overlaps a word boundary. This is determined by the value of ADDR0. When ADDR0
= 0 (an even address), the address is on a word and byte boundary. When ADDR0 =
1 (an odd address), the address is on a byte boundary only. A byte operand is aligned
at any address; a word or long-word operand is misaligned at an odd address.
The largest amount of data that can be transferred by a single bus cycle is an aligned
word. If the MCU transfers a long-word operand through a 16-bit port, the most signif-
icant operand word is transferred on the first bus cycle and the least significant
operand word is transferred on a following bus cycle.
The CPU32 does not support misaligned word transfers. An attempt to do so will result
in an “address error” exception.
Table 4-20
entries are portions of a requested operand that are read or written during a bus cycle
and are defined by SIZ1, SIZ0, and ADDR0 for that bus cycle.
OPERAND
31
shows how operands are aligned for various types of transfers. OPn
OP0
SINGLE-CHIP INTEGRATION MODULE 2 (SCIM2E)
Freescale Semiconductor, Inc.
For More Information On This Product,
Figure 4-10 Operand Byte Order
24
23
Go to: www.freescale.com
Rev. 25 June 03
OP1
OP0
BYTE ORDER
1615
OP2
OP1
OP0
8 7
Table 4-20
OPERAND BYTE ORDER
OP3
OP2
OP1
OP0
also shows
MOTOROLA
0
4-37