MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 353

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

DSSR — Development Support Status Register
8.4.4 Development Support Status Register
MC68F375
REFERENCE MANUAL
Bit(s)
MSB
Bit(s)
15:8
15
2:0
0
4
3
2
1
0
7
6
5
4
3
RESET:
14
0
CHBK
Name
Name
BKPT
PCBK
SRBK
TPUF
BM
BC
BH
BL
BT
—
—
13
0
Channel breakpoint enable
0 = Breakpoint not enabled
1 = Break if CHAN register equals channel breakpoint register at beginning of state or when
Host service breakpoint enable
0 = Breakpoint not enabled
1 = Break if host service latch is asserted at beginning of state
Link service breakpoint enable
0 = Breakpoint not enabled
1 = Break if link service latch is asserted at beginning of state
MRL breakpoint enable
0 = Breakpoint not enabled
1 = Break if MRL is asserted at beginning of state
TDL breakpoint enable
0 = Breakpoint not enabled
1 = Break if TDL is asserted at beginning of state
Reserved
Breakpoint asserted flag. If an internal breakpoint caused the TPU3 to enter the halted state, the
TPU3 asserts the
TPU3 recognizes a breakpoint acknowledge cycle, or until the IMB FREEZE signal is asserted.
counter) register match with the PC breakpoint register. PCBK is negated when the BKPT flag
is cleared.
Channel register breakpoint flag. CHBK is asserted if a breakpoint occurs because of a CHAN
register match with the CHAN register breakpoint register. CHBK is negated when the BKPT flag
is cleared.
Service request breakpoint flag. SRBK is asserted if a breakpoint occurs because of any of the
service request latches being asserted along with their corresponding enable flag in the devel-
opment support control register. SRBK is negated when the BKPT flag is cleared.
TPU3 FREEZE flag. TPUF is set whenever the TPU3 is in a halted state as a result of FREEZE
being asserted. This flag is automatically negated when the TPU3 exits the halted state because
of FREEZE being negated.
Reserved
PC breakpoint flag. PCBK is asserted if a breakpoint occurs because of a PC (microprogram
RESERVED
12
0
CHAN is changed through microcode
Table 8-7 DSCR Bit Settings (Continued)
Freescale Semiconductor, Inc.
11
0
For More Information On This Product,
Table 8-8 DSSR Bit Settings
10
BKPT
0
TIME PROCESSOR UNIT 3
Go to: www.freescale.com
9
0
signal on the IMB and sets the BKPT flag. BKPT remains set until the
Rev. 25 June 03
8
0
BKPT PCBK CHBK SRBK TPUF
7
0
Description
Description
6
0
5
0
4
0
3
0
2
0
0xYF FE06
RESERVED
MOTOROLA
1
0
LSB
8-13
0
0