MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 203

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

MC68F375
REFERENCE MANUAL
Figure 5-8
ator. A 5-bit down counter, clocked at the system clock rate, is used to create both the
high phase and the low phase of the QCLK signal. At the beginning of the high phase,
the 5-bit counter is loaded with the 5-bit PSH value. When the zero detector finds that
the high phase is finished, the QCLK is reset. A 3-bit comparator looks for a one’s com-
plement match with the 3-bit PSL value, which is the end of the low phase of the QCLK.
The PSA bit was maintained for software compatibility, but has no effect on QADC64.
The following equations define Qclk frequency:
The following are equations for calculating the QCLK high and low phases in example
1 shown in
The following are equations for calculating the QCLK high and low phases in example
2 shown in
Where:
• PSH = 0 to 31, the prescaler QCLK high cycles in QACR0
• PSL = 0 to 7, the prescaler QCLK low cycles in QACR0
• F
• F
SYS
QCLK
The guideline for selecting PSH and PSL is select is to maintain
approximately 50% duty cycle. So for prescaler values less then 16,
or PSH
large as possible.
shows that the prescaler is essentially a variable pulse width signal gener-
Figure
Figure
= System clock frequency
= QCLK frequency
QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64
5-9:
5-9:
F
Freescale Semiconductor, Inc.
High QCLK Time = (11 + 1) ÷ 40 x10
PSL. For prescaler values greater than 16 keep PSL as
QCLK
High QCLK Time = (7 + 1) ÷ 32 x 10
Low QCLK Time = (7 + 1) ÷ 32 x 10
Low QCLK Time = (7 + 1) ÷ 40 x10
For More Information On This Product,
= 1 ÷ (High QCLK Time + Low QCLK Time)
High QCLK Time = (PSH + 1) ÷ F
Low QCLK Time = (PSL + 1) ÷ F
F
F
Go to: www.freescale.com
QCLK
QCLK
Rev. 25 June 03
= 1/(300 + 200) = 2 Mhz
= 1/(250 + 250) = 2 Mhz
NOTE
6
6
6
6
= 200 ns
= 250 ns
= 250 ns
SYS
= 300 ns
SYS
MOTOROLA
5-27