MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 363

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

9.1 Introduction
9.2 Features
MC68F375
REFERENCE MANUAL
The dual-port RAM module with TPU microcode storage support (DPTRAM) consists
of a control register block and a 6-Kbyte array of static RAM, which can be used either
as a microcode storage for TPU or as a general-purpose memory.
The DPTRAM module acts as a common memory on the IMB3 and allows the transfer
of data to the two TPU3 modules. Therefore, the DPTRAM interface includes an IMB3
bus interface and two TPU3 interfaces. When the RAM is being used in microcode
mode, the array is only accessible to the TPU3 via a separate local bus, and not via
the IMB3.
The dual-port TPU3 RAM (DPTRAM) is intended to serve as fast, two-clock access,
general-purpose RAM memory for the MCU. When used as general-purpose RAM,
this module is accessed via the MCU’s internal bus.
The DPTRAM module is powered by V
The DPTRAM may also be used as the microcode control store for up to two TPU3
modules when placed in a special emulation mode. In this mode the DPTRAM array
may only be accessed by either or both of the TPU3 units simultaneously via separate
emulation buses, and not via the IMB3. The MC68F375 has only one TPU3.
The DPTRAM contains a multiple input signature calculator (MISC) in order to provide
RAM data corruption checking. The MISC reads each RAM address and generates a
32-bit data-dependent signature. This signature can then be checked by the host.
The DPTRAM supports soft defects detection (SDD).
• Six Kbytes of static RAM
• Only accessible by the CPU if neither TPU3 is in emulation mode
• Low-power stop operation
• TPU microcode mode
— Entered by setting the STOP bit in the DPTMCR
— Applies only to IMB3 accesses and not to accesses from either TPU3 interface
— The DPTRAM array acts as a microcode storage for the TPU module. This
provides a means executing TPU code out of DPTRAM instead of program-
The VDDDPTRAM pin does not have circuitry to allow for standby
operation and should be connected to V
DUAL-PORT TPU RAM (DPTRAM)
Freescale Semiconductor, Inc.
For More Information On This Product,
DUAL-PORT TPU RAM (DPTRAM)
Go to: www.freescale.com
Rev. 25 June 03
SECTION 9
DDL
NOTE
in normal operation.
DDL
.
MOTOROLA
9-1