MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 121

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

4.6.1 Synchronization to CLKOUT
4.6.2 Regular Bus Cycle
MC68F375
REFERENCE MANUAL
External devices connected to the MCU bus can operate at a clock frequency different
from the frequencies of the MCU as long as the external devices satisfy the interface
signal timing constraints. Although bus cycles are classified as asynchronous, they are
interpreted relative to the MCU system clock output (CLKOUT).
Descriptions are made in terms of individual system clock states, labelled {S0, S1,
S2,..., SN}. The designation “state” refers to the logic level of the clock signal, and
does not correspond to any implemented machine state. A clock cycle consists of two
successive states. Refer to
more information.
Bus cycles terminated by DSACK assertion normally require a minimum of three
CLKOUT cycles. To support systems that use CLKOUT to generate DSACK and other
inputs, asynchronous input setup time and asynchronous input hold times are speci-
fied. When these specifications are met, the MCU is guaranteed to recognize the
appropriate signal on a specific edge of the CLKOUT signal.
The following paragraphs contain a discussion of cycles that use external bus control
logic. Refer to
To initiate a transfer, the MCU drives the address bus and the SIZ[1:0] signals. The
SIZ signals and ADDR0 are externally decoded to select the active portion of the data
bus. Refer to
W are valid, a peripheral device either places data on the bus (read cycle) or latches
data from the bus (write cycle), then asserts a DSACK[1:0] combination to indicate the
port size.
The DSACK[1:0] signals can be asserted before the data from a peripheral device is
valid on a read cycle. To ensure valid data is latched by the MCU, a maximum period
between MCU assertion of DS and supplied assertion of DSACK[1:0] is specified.
There is no specified maximum for the period between MCU assertion of AS and sup-
plied assertion of DSACK[1:0]. Although the MCU can transfer data in a minimum of
three clock cycles when the cycle is terminated with DSACK, the MCU inserts wait
cycles in clock period increments until either DSACK1 or DSACK0 goes low.
If the DSACK bus termination signals remain unasserted, the MCU will continue to
insert wait states, and the bus cycle will never end. If no peripheral responds to an
access, or if an access is invalid, external logic should assert the BERR or HALT sig-
nals to abort the bus cycle (when BERR and HALT are asserted simultaneously, the
CPU32 acts as though only BERR is asserted). When enabled, the SCIM2E bus mon-
itor asserts BERR when DSACK response time exceeds a predetermined limit. The
bus monitor timeout period is determined by the BMT[1:0] field in SYPCR. The maxi-
mum bus monitor timeout period is 64 system clock cycles.
4.5.2 Dynamic Bus Sizing
4.6.3 Fast Termination Cycles
SINGLE-CHIP INTEGRATION MODULE 2 (SCIM2E)
Freescale Semiconductor, Inc.
For More Information On This Product,
APPENDIX E ELECTRICAL CHARACTERISTICS
Go to: www.freescale.com
Rev. 25 June 03
for more information. When AS, DS, and R/
for more information.
MOTOROLA
4-39
for