MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 96

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MC68F375BGMZP33

Manufacturer Part Number
MC68F375BGMZP33
Description
IC MPU 32BIT 33MHZ 217-PBGA
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MC68F375BGMZP33

Processor Type
M683xx 32-Bit
Speed
33MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
217-PBGA
Processor Series
M683xx
Core
CPU32
Data Bus Width
32 bit
Program Memory Type
Flash
Program Memory Size
256 KB
Data Ram Size
10 KB
Interface Type
SPI, SCI, CAN
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
48
Number Of Timers
16
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Lead Free Status / Rohs Status
No

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68F375BGMZP33
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
SYNCR — Synthesizer Control Register, Fast Reference Mode
SYNCR — Synthesizer Control Register, Slow Reference Mode
4.3.6 Clock Synthesizer Control Register
MC68F375
REFERENCE MANUAL
MSB
MSB
15
X
RESET:
0
15
X
0
RESET:
EXTAL
When the MC68F375 is configured in external clock mode, the VCO will be turned off
to save power. Changing the unused W bits will have no effect.
The synthesizer control register (SYNCR) is readable and writable in supervisor mode.
The encoding and default value of the upper byte of SYNCR depend on the clock
mode selected at reset.
For slow reference mode, the default value is 0x3F which corresponds to an operating
frequency of 8.38 MHz for a 32.768-KHz crystal. For fast reference mode, the default
value of the upper byte is 0x30, which corresponds to a 2-to-1 match of the reference
frequency. For external clock mode, the default value of the upper byte is 0x80, which
corresponds to an operating frequency equal to the input frequency on EXTAL. The
default value is forced into the SYNCR on reset, along with the default values of the
other bits in the register (all zeros).
The encodings and default reset states of the bits in SYNCR in the three clock modes
are shown below.
14
0
14
W
0
W[2:0]
13
1
13
1
/2
12
1
12
1
11
0
11
1
SINGLE-CHIP INTEGRATION MODULE 2 (SCIM2E)
Y
Freescale Semiconductor, Inc.
10
10
0
1
Y[2:0] Bits
For More Information On This Product,
Figure 4-4 External Clock Mode
(Y<6)
9
1
/(2
9
Y
0
Y
)
8
1
Go to: www.freescale.com
8
0
EDIV
EDIV
Rev. 25 June 03
7
0
7
0
served
served
Re-
6
0
Re-
6
0
LOSCD
LOSCD
X Bit
/(2-X)
5
0
5
0
SLIMP
SLIMP
4
0
4
0
SLOCK
SLOCK
3
1
3
1
/2
RSTEN
RSTEN STSCIM
2
0
2
0
System Clock
STSCIM
0xYF FA04
0xYF FA04
1
0
MOTOROLA
1
0
STEXT
STEXT
LSB
LSB
0
0
4-14
0
0

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