MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 315

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

7.4.3.1 Configuring the TouCAN Bit Timing
7.4.4 Error Counters
MC68F375
REFERENCE MANUAL
configure the bit timing parameters. The prescaler divide register (PRESDIV) allows
the user to select the ratio used to derive the S-clock from the system clock. The time
quanta clock operates at the S-clock frequency.
tem clock, CAN bit rate, and S-clock bit timing parameters. Refer to
Programmer’s Model
The following considerations must be observed when programming bit timing
functions.
The TouCAN has two error counters, the transmit (TX) error counter and the receive
(RX) error counter. Refer to
counters.The rules for increasing and decreasing these counters are described in the
CAN protocol, and are fully implemented in the TouCAN. Each counter has the
following features:
Table 7-8 Example System Clock, CAN Bit Rate and S-Clock Frequencies
System Clock
Frequency
• If the programmed PRESDIV value results in a single system clock per one time
• If the programmed PRESDIV value results in a single system clock per one time
• If the prescaler and bit timing control fields are programmed to values that result
• The TouCAN bit time must be programmed to be greater than or equal to nine
• 8-bit up/down counter
quantum, then the PSEG2 field in CANCTRL2 register must not be programmed
to zero.
quantum, then the information processing time (IPT) equals three time quanta;
otherwise it equals two time quanta. If PSEG2 equals two, then the TouCAN
transmits one time quantum late relative to the scheduled sync segment.
in fewer than 10 system clock periods per CAN bit time and the CAN bus loading
is 100%, then anytime the rising edge of a start-of-frame (SOF) symbol transmit-
ted by another node occurs during the third bit of the intermission between mes-
sages, the TouCAN may not be able to prepare a message buffer for transmission
in time to begin its own transmission and arbitrate against the message which
transmitted the early SOF.
system clocks, or correct operation is not guaranteed.
(MHz)
25
20
16
25
20
16
CAN Bit-Rate
(MHz)
0.125
0.125
0.125
Freescale Semiconductor, Inc.
1
1
1
For More Information On This Product,
for more information on the bit timing registers.
CAN 2.0B CONTROLLER MODULE
7.8 Programmer’s Model
Possible S-Clock
Frequency (MHz)
Go to: www.freescale.com
1, 1.25, 2.5
1, 2, 2.5
10, 20
8, 16
Rev. 25 June 03
1, 2
25
Possible Number of
Time Quanta/Bit
Table 7-8
8, 16, 20
8,10, 20
10, 20
8, 16
8,16
25
for more information on error
provides examples of sys-
PRESDIV Value + 1
25, 20,10
20, 10, 8
16, 8
2, 1
2, 1
1
MOTOROLA
7.8
7-9